Saeed Nejati

Orcid: 0000-0002-1473-3630

According to our database1, Saeed Nejati authored at least 15 papers between 2011 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Publisher Correction: Algorithm selection for SMT.
Int. J. Softw. Tools Technol. Transf., December, 2023

Algorithm selection for SMT.
Int. J. Softw. Tools Technol. Transf., April, 2023

2022
Diversifying a Parallel SAT Solver with Bayesian Moment Matching.
Proceedings of the Dependable Software Engineering. Theories, Tools, and Applications, 2022

2021
MachSMT: A Machine Learning-based Algorithm Selector for SMT Solvers.
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2021

2020
CDCL(Crypto) and Machine Learning based SAT Solvers for Cryptanalysis.
PhD thesis, 2020

Online Bayesian Moment Matching based SAT Solver Heuristics.
Proceedings of the 37th International Conference on Machine Learning, 2020

A Machine Learning Based Splitting Heuristic for Divide-and-Conquer Solvers.
Proceedings of the Principles and Practice of Constraint Programming, 2020

2019
Impact of diminished-1 encoding on residue number systems arithmetic units and converters.
Comput. Electr. Eng., 2019

CDCL(Crypto) SAT solvers for cryptanalysis.
Proceedings of the 29th Annual International Conference on Computer Science and Software Engineering, 2019

2018
Algebraic Fault Attack on SHA Hash Functions Using Programmatic SAT Solvers.
Proceedings of the Principles and Practice of Constraint Programming, 2018

2017
Adaptive Restart and CEGAR-Based Solver for Inverting Cryptographic Hash Functions.
Proceedings of the Verified Software. Theories, Tools, and Experiments, 2017

A Propagation Rate Based Splitting Heuristic for Divide-and-Conquer Solvers.
Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2017 - 20th International Conference, Melbourne, VIC, Australia, August 28, 2017

2016
Non-Deterministic Timers for Hardware Trojan Activation (or How a Little Randomness Can Go the Wrong Way).
Proceedings of the 10th USENIX Workshop on Offensive Technologies, 2016

MathCheck2: A SAT+CAS Verifier for Combinatorial Conjectures.
Proceedings of the 1st Workshop on Satisfiability Checking and Symbolic Computation co-located with 18th International Symposium on Symbolic and Numeric Algorithms for Scientific Computing (SYNASC 2016), 2016

2011
On building general modular adders from standard binary arithmetic components.
Proceedings of the Conference Record of the Forty Fifth Asilomar Conference on Signals, 2011


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