Ding-Ming Kwai

Masahiro Aoyagi

Meng-Fan Marvin Chang

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Enabling inter-die co-optimization in 3-D IC with TSVs.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

Worst-case IR-drop monitoring with 1GHz sampling rate.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

A case study: 3-D stacked memory system architecture exploration by ESL virtual platform.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

An FPGA-based test platform for analyzing data retention time distribution of DRAMs.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

Benchmarking for research in power delivery networks of three-dimensional integrated circuits.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Physical Design, 2013

I-LUTSim: An iterative look-up table based thermal simulator for 3-D ICs.

[BibT_eX]

[DOI]

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

An MCT-Based Bit-Weight Extraction Technique for Embedded SAR ADC Testing and Calibration.

[BibT_eX]

[DOI]

J. Electron. Test., 2012

A SAR ADC missing-decision level detection and removal technique.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE VLSI Test Symposium, 2012

3-D centric technology and realization with TSV.

[BibT_eX]

[DOI]

Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

3D-IC BISR for stacked memories using cross-die spares.

[BibT_eX]

[DOI]

Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

A built-in self-test scheme for 3D RAMs.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Test Conference, 2012

Small delay testing for TSVs in 3-D ICs.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Capturing the phantom of the power grid - on the runtime adaptive techniques for noise reduction.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Yield Enhancement by Bad-Die Recycling and Stacking With Though-Silicon Vias.

[BibT_eX]

[DOI]

Yung-Fa Chou

IEEE Trans. Very Large Scale Integr. Syst., 2011

A built-in self-test scheme for the post-bond test of TSVs in 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

3D Stacked IC layout considering bond pad density and doubling for manufacturing yield improvement.

[BibT_eX]

[DOI]

Chang-Tzu Lin

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Developing through-silicon stacking process using 3-D CMOS imager as a test vehicle.

[BibT_eX]

[DOI]

Ka-Yi Yeh

Proceedings of the International SoC Design Conference, 2011

A Pre- and Post-bond Self-Testing and Calibration Methodology for SAR ADC Array in 3-D CMOS Imager.

[BibT_eX]

[DOI]

Proceedings of the 16th European Test Symposium, 2011

Thermal-aware on-line task allocation for 3D multi-core processor throughput optimization.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

A self-testing and calibration method for embedded successive approximation register ADC.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

On-chip testing of blind and open-sleeve TSVs for 3D IC before bonding.

[BibT_eX]

[DOI]

Po-Yuan Chen

Proceedings of the 28th IEEE VLSI Test Symposium, 2010

An error tolerance scheme for 3D CMOS imagers.

[BibT_eX]

[DOI]

Hsiu-Ming Chang

Jiun-Lang Huang

Kwang-Ting (Tim) Cheng

Proceedings of the 47th Design Automation Conference, 2010

Performance Characterization of TSV in 3D IC via Sensitivity Analysis.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE Asian Test Symposium, 2010

A Test Integration Methodology for 3D Integrated Circuits.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE Asian Test Symposium, 2010

CAD reference flow for 3D via-last integrated circuits.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Homogeneous integration for 3D IC with TSV.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

On-Chip TSV Testing for 3D IC before Bonding Using Sense Amplification.

[BibT_eX]

[DOI]

Po-Yuan Chen

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2006

SRAM Cell Current in Low Leakage Design.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Workshop on Memory Technology, 2006

FlexiVia ROM Compiler Programmable on Different Via Layers Based on Top Metal Assignment.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Workshop on Memory Technology, 2006

2005

Measurement and characterization of 6T SRAM cell current.

[BibT_eX]

[DOI]

Ching-Hua Hsiao

Proceedings of the 13th IEEE International Workshop on Memory Technology, 2005

Via-programmable read-only memory design for full code coverage using a dynamic bit-line shielding technique.

[BibT_eX]

[DOI]

Meng-Fan Chang

Kuei-Ann Wen

Proceedings of the 13th IEEE International Workshop on Memory Technology, 2005

2004

Comparing four classes of torus-based parallel architectures: Networkparameters and communication performance.

[BibT_eX]

[DOI]

Math. Comput. Model., 2004

Incomplete <i>k</i>-ary <i>n</i>-cube and its derivatives.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2004

Supply and Substrate Noise Tolerance Using Dynamic Tracking Clusters in Configurable Memory Designs.

[BibT_eX]

[DOI]

Meng-Fan Chang

Kuei-Ann Wen

Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

2003

Practical considerations in applying Σ-Δ modulation-based analog BIST to sampled-data systems.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2003

Parallel Architectures and Adaptation Algorithms for Programmable FIR Digital Filters With Fully Pipelined Data and Control Flows.

[BibT_eX]

[DOI]

J. Inf. Sci. Eng., 2003

2001

Scalable Linear Array Architecture with Data-Driven Control for Ultrahigh-Speed Vector Quantization.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2001

A Unified Formulation of Honeycomb and Diamond Networks.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2001

2000

Characterization and Generalization of Honeycomb and Diamond Networks.

[BibT_eX]

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000

etection of SRAM cell stability by lowering array supply voltage.

[BibT_eX]

[DOI]

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999

Scalability of Programmable FIR Digital Filters.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 1999

Correction to 'Periodically Regular Chordal Rings'.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 1999

Periodically Regular Chordal Rings.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 1999

Data-Driven Control Scheme for Linear Arrays: Application to a Stable Insertion Sorter.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 1999

1998

Pruned Three-Dimensional Toroidal Networks.

[BibT_eX]

[DOI]

Inf. Process. Lett., 1998

Tight Bounds on the Diameter of Gaussian Cubes.

[BibT_eX]

[DOI]

Comput. J., 1998

1997

An on-line fault diagnosis scheme for linear processor arrays.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 1997

A Class of Fixed-Degree Cayley-Graph Interconnection Networks Derived by Pruning k-ary n-cubes.

[BibT_eX]

[DOI]

Proceedings of the 1997 International Conference on Parallel Processing (ICPP '97), 1997

1996

FFT computation with linear processor arrays using a data-driven control scheme.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 1996

A Generalization of Hypercubic Networks Based on their Chordal Ring Structures.

[BibT_eX]

[DOI]

Parallel Process. Lett., 1996

Periodically regular chordal rings: generality, scalability, and VLSI layout.

[BibT_eX]

[DOI]

Proceedings of the Eighth IEEE Symposium on Parallel and Distributed Processing, 1996

Comparing the Performance Parameters of Two Network Structures for Scalable Massively Parallel Processors.

[BibT_eX]

[DOI]

Proceedings of the MASCOTS '96, 1996

1992

Data Flow Representation of Iterative Algorithms for Systolic Arrays.

[BibT_eX]

[DOI]

Chein-Wei Jen

IEEE Trans. Computers, 1992

1989

Multi-dimensional parallel computing structures for regular iterative algorithms.

[BibT_eX]

[DOI]

Chein-Wei Jen