Ben Perach

According to our database, Ben Perach authored at least 13 papers between 2018 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Understanding Bulk-Bitwise Processing In-Memory Through Database Analytics.

Ben Perach, Ronny Ronen, Benny Kimelfeld, Shahar Kvatinsky

IEEE Trans. Emerg. Top. Comput., 2024

2023

ClaPIM: Scalable Sequence Classification Using Processing-in-Memory.

Marcel Khalifa, Barak Hoffer, Orian Leitersdorf, Robert Hanhan, Ben Perach, Leonid Yavits, Shahar Kvatinsky

IEEE Trans. Very Large Scale Integr. Syst., September, 2023

Enabling Relational Database Analytical Processing in Bulk-Bitwise Processing-In-Memory.

Ben Perach, Ronny Ronen, Shahar Kvatinsky

Proceedings of the 36th IEEE International System-on-Chip Conference, 2023

Accelerating Relational Database Analytical Processing with Bulk-Bitwise Processing-in-Memory.

Ben Perach, Ronny Ronen, Shahar Kvatinsky

Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

On Consistency for Bulk-Bitwise Processing-in-Memory.

Ben Perach, Ronny Ronen, Shahar Kvatinsky

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

2022

The Bitlet Model: A Parameterized Analytical Model to Compare PIM and CPU Systems.

Ronny Ronen, Adi Eliahu, Orian Leitersdorf, Natan Peled, Kunal Korgaonkar, Anupam Chattopadhyay, Ben Perach, Shahar Kvatinsky

ACM J. Emerg. Technol. Comput. Syst., 2022

PIMDB: Understanding Bulk-Bitwise Processing In-Memory Through Database Analytics.

Ben Perach, Ronny Ronen, Benny Kimelfeld, Shahar Kvatinsky

CoRR, 2022

2021

Efficient Error-Correcting-Code Mechanism for High-Throughput Memristive Processing-in-Memory.

Orian Leitersdorf, Ben Perach, Ronny Ronen, Shahar Kvatinsky

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2019

An Asynchronous and Low-Power True Random Number Generator Using STT-MTJ.

Ben Perach, Shahar Kvatinsky

IEEE Trans. Very Large Scale Integr. Syst., 2019

CONCEPT: A Column-Oriented Memory Controller for Efficient Memory and PIM Operations in RRAM.

Nishil Talati, Heonjae Ha, Ben Perach, Ronny Ronen, Shahar Kvatinsky

IEEE Micro, 2019

MTJ-Based Hardware Synapse Design for Quantized Deep Neural Networks.

Tzofnat Greenberg-Toledo, Ben Perach, Daniel Soudry, Shahar Kvatinsky

CoRR, 2019

STT-ANGIE: Asynchronous True Random Number GEnerator Using STT-MTJ.

Ben Perach, Shahar Kvatinsky

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018

SiMT-DSP: A Massively Multithreaded DSP Architecture.

Ben Perach, Shlomo Weiss

IEEE Trans. Very Large Scale Integr. Syst., 2018