Leonid Yavits

According to our database, Leonid Yavits authored at least 53 papers between 2013 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

ViTAL: Vision TrAnsformer based Low coverage SARS-CoV-2 lineage assignment.

Zuher Jahshan, Leonid Yavits

Bioinform., March, 2024

DRAMA: Commodity DRAM Based Content Addressable Memory.

Leonid Yavits

IEEE Comput. Archit. Lett., 2024

MajorK: Majority Based kmer Matching in Commodity DRAM.

Zuher Jahshan, Leonid Yavits

IEEE Comput. Archit. Lett., 2024

ViRAL: Vision Transformer Based Accelerator for ReAL Time Lineage Assignment of Viral Pathogens.

Zuher Jahshan, Esteban Garzón, Leonid Yavits

IEEE Access, 2024

FASTA: Revisiting Fully Associative Memories in Computer Microarchitecture.

Esteban Garzón, Robert Hanhan, Marco Lanuzza, Adam Teman, Leonid Yavits

IEEE Access, 2024

2023

A Low-Complexity Sensing Scheme for Approximate Matching Content-Addressable Memory.

Esteban Garzón, Roman Golman, Marco Lanuzza, Adam Teman, Leonid Yavits

IEEE Trans. Circuits Syst. II Express Briefs, October, 2023

ClaPIM: Scalable Sequence Classification Using Processing-in-Memory.

Marcel Khalifa, Barak Hoffer, Orian Leitersdorf, Robert Hanhan, Ben Perach, Leonid Yavits, Shahar Kvatinsky

IEEE Trans. Very Large Scale Integr. Syst., September, 2023

AM⁴: MRAM Crossbar Based CAM/TCAM/ACAM/AP for In-Memory Computing.

Esteban Garzón, Marco Lanuzza, Adam Teman, Leonid Yavits

IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023

A Low-Energy DMTJ-Based Ternary Content- Addressable Memory With Reliable Sub-Nanosecond Search Operation.

Esteban Garzón, Leonid Yavits, Giovanni Finocchio, Mario Carpentieri, Adam Teman, Marco Lanuzza

IEEE Access, 2023

DASH-CAM: Dynamic Approximate SearcH Content Addressable Memory for genome classification.

Zuher Jahshan, Itay Merlin, Esteban Garzón, Leonid Yavits

Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

STT-MRAM Technology For Energy-Efficient Cryogenic Memory Applications.

Esteban Garzón, Leonid Yavits, Adam Teman, Marco Lanuzza

Proceedings of the 14th IEEE Latin America Symposium on Circuits and System, 2023

2022

GIRAF: General Purpose In-Storage Resistive Associative Framework.

Leonid Yavits, Roman Kaplan, Ran Ginosar

IEEE Trans. Parallel Distributed Syst., 2022

AIDA: Associative In-Memory Deep Learning Accelerator.

Esteban Garzón, Adam Teman, Marco Lanuzza, Leonid Yavits

IEEE Micro, 2022

CoViT: Real-time phylogenetics for the SARS-CoV-2 pandemic using Vision Transformers.

Zuher Jahshan, Leonid Yavits

CoRR, 2022

Hamming Distance Tolerant Content-Addressable Memory (HD-CAM) for DNA Classification.

Esteban Garzón, Roman Golman, Zuher Jahshan, Robert Hanhan, Natan Vinshtok-Melnik, Marco Lanuzza, Adam Teman, Leonid Yavits

IEEE Access, 2022

EDAM: edit distance tolerant approximate matching content addressable memory.

Robert Hanhan, Esteban Garzón, Zuher Jahshan, Adam Teman, Marco Lanuzza, Leonid Yavits

Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

2021

Hamming Distance Tolerant Content-Addressable Memory (HD-CAM) for Approximate Matching Applications.

Esteban Garzón, Roman Golman, Zuher Jahshan, Robert Hanhan, Natan Vinshtok-Melnik, Marco Lanuzza, Adam Teman, Leonid Yavits

CoRR, 2021

FiltPIM: In-Memory Filter for DNA Sequencing.

Marcel Khalifa, Rotem Ben Hur, Ronny Ronen, Orian Leitersdorf, Leonid Yavits, Shahar Kvatinsky

Proceedings of the 28th IEEE International Conference on Electronics, 2021

2020

BioSEAL: In-Memory Biological Sequence Alignment Accelerator for Large-Scale Genomic Data.

Roman Kaplan, Leonid Yavits, Ran Ginosar

Proceedings of the SYSTOR 2020: The 13th ACM International Systems and Storage Conference, 2020

Dual Mode Logic Address Decoder.

Leonid Yavits, Ramiro Taco, Netanel Shavit, Inbal Stanger, Alexander Fish

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Exploiting Single-Well Design for Energy-Efficient Ultra-Wide Voltage Range Dual Mode Logic-Based Digital Circuits in 28nm FD-SOI Technology.

Ramiro Taco, Leonid Yavits, Netanel Shavit, Inbal Stanger, Marco Lanuzza, Alexander Fish

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Robust Dual Mode Pass Logic (DMPL) for Energy Efficiency and High Performance.

Inbal Stanger, Netanel Shavit, Ramiro Taco, Leonid Yavits, Marco Lanuzza, Alexander Fish

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

WoLFRaM: Enhancing Wear-Leveling and Fault Tolerance in Resistive Memories using Programmable Address Decoders.

Leonid Yavits, Lois Orosa, Suyash Mahar, João Dinis Ferreira, Mattan Erez, Ran Ginosar, Onur Mutlu

Proceedings of the 38th IEEE International Conference on Computer Design, 2020

2019

RASSA: Resistive Prealignment Accelerator for Approximate DNA Long Read Mapping.

Roman Kaplan, Leonid Yavits, Ran Ginosar

IEEE Micro, 2019

AIDA: Associative DNN Inference Accelerator.

Leonid Yavits, Roman Kaplan, Ran Ginosar

CoRR, 2019

POSTER: GIRAF: General Purpose In-Storage Resistive Associative Framework.

Leonid Yavits, Roman Kaplan, Ran Ginosar

Proceedings of the 28th International Conference on Parallel Architectures and Compilation Techniques, 2019

POSTER: BioSEAL: In-Memory Biological Sequence Alignment Accelerator for Large-Scale Genomic Data.

Roman Kaplan, Leonid Yavits, Ran Ginosar

Proceedings of the 28th International Conference on Parallel Architectures and Compilation Techniques, 2019

2018

Enabling Full Associativity with Memristive Address Decoder.

Leonid Yavits, Roman Kaplan, Ran Ginosar

IEEE Micro, 2018

RASSA: Resistive Accelerator for Approximate Long Read DNA Mapping.

Roman Kaplan, Leonid Yavits, Ran Ginosar

CoRR, 2018

PRINS: Resistive CAM Processing in Storage.

Leonid Yavits, Roman Kaplan, Ran Ginosar

CoRR, 2018

Accelerator for Sparse Machine Learning.

Leonid Yavits, Ran Ginosar

IEEE Comput. Archit. Lett., 2018

2017

From Processing-in-Memory to Processing-in-Storage.

Roman Kaplan, Leonid Yavits, Ran Ginosar

Supercomput. Front. Innov., 2017

A Resistive CAM Processing-in-Storage Architecture for DNA Sequence Alignment.

Roman Kaplan, Leonid Yavits, Ran Ginosar, Uri C. Weiser

IEEE Micro, 2017

MultiAmdahl: Optimal Resource Allocation in Heterogeneous Architectures.

Leonid Yavits, Amir Morad, Uri C. Weiser, Ran Ginosar

CoRR, 2017

Sparse Matrix Multiplication on CAM Based Accelerator.

Leonid Yavits, Ran Ginosar

CoRR, 2017

Resistive Address Decoder.

Leonid Yavits, Uri C. Weiser, Ran Ginosar

IEEE Comput. Archit. Lett., 2017

2016

The Effect of Temperature on Amdahl Law in 3D Multicore Era.

Leonid Yavits, Amir Morad, Ran Ginosar

IEEE Trans. Computers, 2016

Resistive GP-SIMD Processing-In-Memory.

Amir Morad, Leonid Yavits, Shahar Kvatinsky, Ran Ginosar

ACM Trans. Archit. Code Optim., 2016

Convex Optimization of Real Time SoC.

Leonid Yavits, Amir Morad, Ran Ginosar, Uri C. Weiser

CoRR, 2016

Effect of Data Sharing on Private Cache Design in Chip Multiprocessors.

Leonid Yavits, Amir Morad, Ran Ginosar

CoRR, 2016

Deduplication in resistive content addressable memory based solid state drive.

Roman Kaplan, Leonid Yavits, Amir Morad, Ran Ginosar

Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

2015

Sparse Matrix Multiplication On An Associative Processor.

Leonid Yavits, Amir Morad, Ran Ginosar

IEEE Trans. Parallel Distributed Syst., 2015

Computer Architecture with Associative Processor Replacing Last-Level Cache and SIMD Accelerator.

Leonid Yavits, Amir Morad, Ran Ginosar

IEEE Trans. Computers, 2015

Resistive Associative Processor.

Leonid Yavits, Shahar Kvatinsky, Amir Morad, Ran Ginosar

IEEE Comput. Archit. Lett., 2015

2014

GP-SIMD Processing-in-Memory.

Amir Morad, Leonid Yavits, Ran Ginosar

ACM Trans. Archit. Code Optim., 2014

The effect of communication and synchronization on Amdahl's law in multicore systems.

Leonid Yavits, Amir Morad, Ran Ginosar

Parallel Comput., 2014

Cache Hierarchy Optimization.

Leonid Yavits, Amir Morad, Ran Ginosar

IEEE Comput. Archit. Lett., 2014

Generalized MultiAmdahl: Optimization of Heterogeneous Multi-Accelerator SoC.

Amir Morad, Tomer Y. Morad, Leonid Yavits, Ran Ginosar, Uri C. Weiser

IEEE Comput. Archit. Lett., 2014

Convex optimization of resource allocation in asymmetric and heterogeneous SoC.

Amir Morad, Leonid Yavits, Ran Ginosar

Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014

Efficient Dense and Sparse Matrix Multiplication on GP-SIMD.

Amir Morad, Leonid Yavits, Ran Ginosar

Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014

2013

Thermal analysis of 3D associative processor.

Leonid Yavits, Amir Morad, Ran Ginosar

CoRR, 2013

The Effect of Communication and Synchronization on Amdahl Law in Multicore Systems.

Leonid Yavits, Amir Morad, Ran Ginosar

CoRR, 2013

3D cache hierarchy optimization.

Leonid Yavits, Amir Morad, Ran Ginosar

Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013