Biswajit Bhowmik

J. Electron. Test., 2020

Test Methodology for Analysis of Coexistent Logic-Level Faults in NoC Channels.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE International Conference on Systems, Man, and Cybernetics, 2020

Improving Reliability in Spidergon Network on Chip-Microprocessors.

[BibT_eX]

[DOI]

Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

Locating Open-Channels in Octagon Networks on Chip-Microprocessors.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

Reliability Monitoring in a Smart NoC Component.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

2019

Performance-Aware Test Scheduling for Diagnosing Coexistent Channel Faults in Topology-Agnostic Networks-on-Chip.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2019

A Power-Aware Fault Detection Scheme for 2D Mesh-Based Network-on-Chip Interconnects.

[BibT_eX]

[DOI]

J. Low Power Electron., 2019

A Low-Cost Test Solution for Reliable Communication in Networks-on-Chip.

[BibT_eX]

[DOI]

J. Electron. Test., 2019

2018

Reliability-Aware Test Methodology for Detecting Short-Channel Faults in On-Chip Networks.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

On-Line Analysis of Stuck-at Faults in On-Chip Network Interconnects.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2018

Heaping of Sorrow Upon Sorrow.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2018

A Time-optimized Test-Solution Scheme for the Analysis of Permanent Faults on NoC Interconnects.

[BibT_eX]

[DOI]

Proceedings of the 8th International Symposium on Embedded Computing and System Design, 2018

2017

A Time-Optimized Scheme Towards Analysis of Channel-Shorts in on-Chip Networks.

[BibT_eX]

[DOI]

J. Electron. Test., 2017

Charka: A reliability-aware test scheme for diagnosis of channel shorts beyond mesh NoCs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016

On-line detection and diagnosis of stuck-at faults in channels of NoC-based systems.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Conference on Systems, Man, and Cybernetics, 2016

A topology-agnostic test model for link shorts in on-chip networks.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Conference on Systems, Man, and Cybernetics, 2016

One poison is antidote against another poison.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Conference on Systems, Man, and Cybernetics, 2016

Detecting and diagnosing open faults in NoC channels on activation of diagonal nodes.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Conference on Systems, Man, and Cybernetics, 2016

Towards a Scalable Test Solution for the Analysis of Interconnect Shorts in On-chip Networks.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on Modeling, 2016

An on-line test solution for addressing interconnect shorts in on-chip networks.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

An odd-even scheme to prevent a packet from being corrupted and dropped in fault tolerant NoCs.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

When Clustering Shows Optimality towards Analyzing Stuck-at Faults in Channels of On-chip Networks.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Conference on High Performance Computing and Communications; 14th IEEE International Conference on Smart City; 2nd IEEE International Conference on Data Science and Systems, 2016

A Reliability-Aware Topology-Agnostic Test Scheme for Detecting, and Diagnosing Interconnect Shorts in On-chip Networks.

[BibT_eX]

[DOI]

2015

Directed Symbolic Execution for VLSI Circuits.

[BibT_eX]

[DOI]