Jatindra Kumar Deka

According to our database, Jatindra Kumar Deka authored at least 42 papers between 1999 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Incomplete Testing of SOC.

Kunwer Mrityunjay Singh, Jatindra Kumar Deka, Santosh Biswas

J. Electron. Test., June, 2023

2021

Retesting Defective Circuits to Allow Acceptable Faults for Yield Enhancement.

Sisir Kumar Jena, Santosh Biswas, Jatindra Kumar Deka

J. Electron. Test., 2021

ATPG for Incomplete Testing of SOC Considering Bridging Faults.

Kunwer Mrityunjay Singh, Santosh Biswas, Jatindra Kumar Deka

Proceedings of the IEEE Region 10 Conference, 2021

Conversion of Virtual Lab Experiments using FOSS: A Case Study of Virtual Labs by NMEICT.

Nanu Alan Kachari, Santosh Biswas, Jatindra Kumar Deka

Proceedings of the 2021 IEEE International Conference on Engineering, 2021

Selective Fault-Masking for Improving Yield and Performance of On-Chip Networks.

Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas

Proceedings of the 2021 IEEE International Conference on Systems, Man, and Cybernetics, 2021

2020

An Efficient Test Set Construction Scheme for Multiple Missing-Gate Faults in Reversible Circuits.

Mousum Handique, Jatindra Kumar Deka, Santosh Biswas

J. Electron. Test., 2020

Approximate Testing of Digital VLSI Circuits using Error Significance based Fault Analysis.

Sisir Kumar Jena, Santosh Biswas, Jatindra Kumar Deka

Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

Maximizing Yield through Retesting of Rejected Circuits using Approximation Technique.

Sisir Kumar Jena, Santosh Biswas, Jatindra Kumar Deka

Proceedings of the 2020 IEEE Region 10 Conference, 2020

A Fault Detection Scheme for Reversible Circuits using -Ve Control k-CNOT Based Circuit.

Mousum Handique, Jatindra Kumar Deka, Santosh Biswas

Proceedings of the 2020 IEEE Region 10 Conference, 2020

Test Methodology for Analysis of Coexistent Logic-Level Faults in NoC Channels.

Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka

Proceedings of the 2020 IEEE International Conference on Systems, Man, and Cybernetics, 2020

Improving Reliability in Spidergon Network on Chip-Microprocessors.

Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas

Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

Locating Open-Channels in Octagon Networks on Chip-Microprocessors.

Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka, Bhargab B. Bhattacharya

Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

Reliability Monitoring in a Smart NoC Component.

Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas

Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

2019

Performance-Aware Test Scheduling for Diagnosing Coexistent Channel Faults in Topology-Agnostic Networks-on-Chip.

Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas, Bhargab B. Bhattacharya

ACM Trans. Design Autom. Electr. Syst., 2019

Test Generation for Bridging Faults in Reversible Circuits Using Path-Level Expressions.

Mousum Handique, Santosh Biswas, Jatindra Kumar Deka

J. Electron. Test., 2019

A Low-Cost Test Solution for Reliable Communication in Networks-on-Chip.

Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka, Bhargab B. Bhattacharya

J. Electron. Test., 2019

Systematic Design of Approximate Adder Using Significance Based Gate-Level Pruning (SGLP) for Image Processing Application.

Sisir Kumar Jena, Santosh Biswas, Jatindra Kumar Deka

Proceedings of the Pattern Recognition and Machine Intelligence, 2019

2018

Reliability-Aware Test Methodology for Detecting Short-Channel Faults in On-Chip Networks.

Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka, Bhargab B. Bhattacharya

IEEE Trans. Very Large Scale Integr. Syst., 2018

On-Line Analysis of Stuck-at Faults in On-Chip Network Interconnects.

Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas

J. Circuits Syst. Comput., 2018

2017

A Time-Optimized Scheme Towards Analysis of Channel-Shorts in on-Chip Networks.

Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas

J. Electron. Test., 2017

Charka: A reliability-aware test scheme for diagnosis of channel shorts beyond mesh NoCs.

Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016

On-line detection and diagnosis of stuck-at faults in channels of NoC-based systems.

Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas, Bhargab B. Bhattacharya

Proceedings of the 2016 IEEE International Conference on Systems, Man, and Cybernetics, 2016

A topology-agnostic test model for link shorts in on-chip networks.

Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas, Bhargab B. Bhattacharya

Proceedings of the 2016 IEEE International Conference on Systems, Man, and Cybernetics, 2016

One poison is antidote against another poison.

Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka, Bhargab B. Bhattacharya

Proceedings of the 2016 IEEE International Conference on Systems, Man, and Cybernetics, 2016

Detecting and diagnosing open faults in NoC channels on activation of diagonal nodes.

Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka, Bhargab B. Bhattacharya

Proceedings of the 2016 IEEE International Conference on Systems, Man, and Cybernetics, 2016

Towards a Scalable Test Solution for the Analysis of Interconnect Shorts in On-chip Networks.

Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas

Proceedings of the 24th IEEE International Symposium on Modeling, 2016

An on-line test solution for addressing interconnect shorts in on-chip networks.

Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas

Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

An odd-even scheme to prevent a packet from being corrupted and dropped in fault tolerant NoCs.

Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka

Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

When Clustering Shows Optimality towards Analyzing Stuck-at Faults in Channels of On-chip Networks.

Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas

Proceedings of the 18th IEEE International Conference on High Performance Computing and Communications; 14th IEEE International Conference on Smart City; 2nd IEEE International Conference on Data Science and Systems, 2016

A Reliability-Aware Topology-Agnostic Test Scheme for Detecting, and Diagnosing Interconnect Shorts in On-chip Networks.

Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka

Proceedings of the 18th IEEE International Conference on High Performance Computing and Communications; 14th IEEE International Conference on Smart City; 2nd IEEE International Conference on Data Science and Systems, 2016

2015

Directed Symbolic Execution for VLSI Circuits.

Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas

Proceedings of the 2015 IEEE International Conference on Systems, 2015

An Optimal Diagnosis of NoC Interconnects on Activation of Diagonal Routers.

Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka

Proceedings of the 2015 IEEE International Conference on Systems, 2015

A packet address driven test strategy for stuck-at faults in networks-on-chip interconnects.

Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka

Proceedings of the 23rd Mediterranean Conference on Control and Automation, 2015

Reliability on Top of Best Effort Delivery: Maximal Connectivity Test on NoC Interconnects.

Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas

Proceedings of the 8th Annual ACM India Conference, Ghaziabad, India, October 29-31, 2015, 2015

2014

Detection of faulty interswitch links in 2-D mesh network-on-chips.

Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka

Proceedings of the 2014 IEEE International Conference on Advanced Networks and Telecommuncations Systems, 2014

2010

Fair diagnosability in PN-based DES models.

Khan Ajoy, Kushagra Misra, Santosh Biswas, Jatindra Kumar Deka, Hemangee K. Kapoor

Proceedings of the 8th IEEE International Conference on Control and Automation, 2010

2005

Variable Ordering of BDDs using Genetic Algorithm.

Moi Riba, Jatindra Kumar Deka

Proceedings of the 2nd Indian International Conference on Artificial Intelligence, 2005

2003

Reasoning about Extremal Properties of Events.

Jatindra Kumar Deka

Proceedings of the 10th International Symposium on Temporal Representation and Reasoning / 4th International Conference on Temporal Logic (TIME-ICTL 2003), 2003

2001

Min-max Computation Tree Logic.

Pallab Dasgupta, P. P. Chakrabarti, Jatindra Kumar Deka, Sriram Sankaranarayanan

Artif. Intell., 2001

Abstractions for model checking of event timings.

Jatindra Kumar Deka, S. Chaki, Pallab Dasgupta, P. P. Chakrabarti

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000

Model checking on timed-event structures.

Pallab Dasgupta, Jatindra Kumar Deka, Partha Pratim Chakrabarti

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

1999

An Efficiently Checkable Subset of TCTL for Formal Verification of Transition Systems with Delays.

Jatindra Kumar Deka, Pallab Dasgupta, P. P. Chakrabarti

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999