Bhargab B. Bhattacharya

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2023

Tracking patellar osteophytes to detect osteoarthritis.

[BibT_eX]

[DOI]

Sabyasachi Mukherjee

Comput. methods Biomech. Biomed. Eng. Imaging Vis., September, 2023

Test Optimization in Memristor Crossbars Based on Path Selection.

[BibT_eX]

[DOI]

Manobendra Nath Mondal

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

2022

Demand-Driven Multi-Target Sample Preparation on Resource-Constrained Digital Microfluidic Biochips.

[BibT_eX]

[DOI]

Shao-Yun Fang

ACM Trans. Design Autom. Electr. Syst., 2022

Mixing Models as Integer Factorization: A Key to Sample Preparation With Microfluidic Biochips.

[BibT_eX]

[DOI]

Debraj Kundu

Sohini Saha

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Efficient Regulation of Synthetic Biocircuits Using Droplet-Aliquot Operations on MEDA Biochips.

[BibT_eX]

[DOI]

Mohamed Ibrahim

Zhanwei Zhong

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

DFT with Universal Test Set for All Missing Gate Faults in Reversible Circuits.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2022

A Framework for Automated Correctness Checking of Biochemical Protocol Realizations on Digital Microfluidic Biochips.

[BibT_eX]

[DOI]

CoRR, 2022

Improved Upper Bound on Independent Domination Number for Hypercubes.

[BibT_eX]

[DOI]

Debabani Chowdhury

CoRR, 2022

Easily-Verifiable Design of Non-Scan Sequential Machines for Conformance Checking.

[BibT_eX]

[DOI]

Habibur Rahaman

Santanu Chattopadhyay

Indranil Sengupta

Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022

On the Construction of Planar Embedding for a Class of Orthogonal Polyhedra.

[BibT_eX]

[DOI]

Nilanjana Karmakar

Proceedings of the Combinatorial Image Analysis - 21st International Workshop, 2022

2021

A survey of digital circuit testing in the light of machine learning.

[BibT_eX]

[DOI]

WIREs Data Mining Knowl. Discov., 2021

Robust Multi-Target Sample Preparation on MEDA Biochips Obviating Waste Production.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2021

SIMOP: A SIMulation-Guided OPtimization Mechanism for Sample Preparation with Digital Microfluidic Biochip.

[BibT_eX]

[DOI]

SN Comput. Sci., 2021

A framework for end-to-end verification for digital microfluidics.

[BibT_eX]

[DOI]

Innov. Syst. Softw. Eng., 2021

Fast algorithms for test optimization of core based 3D SoC.

[BibT_eX]

[DOI]

Integr., 2021

Sample Preparation Meets Farey Sequence: A New Design Technique for Free-Flowing Microfluidic Networks.

[BibT_eX]

[DOI]

CoRR, 2021

2020

Harnessing the Granularity of Micro-Electrode-Dot-Array Architectures for Optimizing Droplet Routing in Biochips.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2020

Architectural Design of Flow-Based Microfluidic Biochips for Multi-Target Dilution of Biochemical Fluids.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2020

A Methodology for Root-Causing In-field Attacks on Microfluidic Executions.

[BibT_eX]

[DOI]

Trans. Comput. Sci., 2020

Test Generation for Flow-Based Microfluidic Biochips With General Architectures.

[BibT_eX]

[DOI]

Chunfeng Liu

Bing Li

Ulf Schlichtmann

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Storage-Aware Algorithms for Dilution and Mixture Preparation With Flow-Based Lab-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Current Comparator-Based Reconfigurable Adder and Multiplier on Hybrid Memristive Crossbar.

[BibT_eX]

[DOI]

Manobendra Nath Mondal

Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

Locating Open-Channels in Octagon Networks on Chip-Microprocessors.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

Sample Preparation with Free-Flowing Biochips using Microfluidic Binary-Tree Network.

[BibT_eX]

[DOI]

Yong-Ak Song

Ajymurat Orozaliev

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

LoPher: SAT-Hardened Logic Embedding on Block Ciphers.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

Performance-Aware Test Scheduling for Diagnosing Coexistent Channel Faults in Topology-Agnostic Networks-on-Chip.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2019

Predicting X-Sensitivity of Circuit-Inputs on Test-Coverage: A Machine-Learning Approach.

[BibT_eX]

[DOI]

Bhaswar B. Bhattacharya

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Error-Oblivious Sample Preparation With Digital Microfluidic Lab-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Optimization of Multi-Target Sample Preparation On-Demand With Digital Microfluidic Biochips.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Efficient Generation of Dilution Gradients With Digital Microfluidic Biochips.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Bone-Cancer Assessment and Destruction Pattern Analysis in Long-Bone X-ray Image.

[BibT_eX]

[DOI]

J. Digit. Imaging, 2019

Maximal Defect-Free Component in Nanoscale Crossbar Circuits Amidst Stuck-Open and Stuck-Closed Faults.

[BibT_eX]

[DOI]

Malay Kule

J. Circuits Syst. Comput., 2019

Scheduling algorithms for reservoir- and mixer-aware sample preparation with microfluidic biochips.

[BibT_eX]

[DOI]

Integr., 2019

A Low-Cost Test Solution for Reliable Communication in Networks-on-Chip.

[BibT_eX]

[DOI]

J. Electron. Test., 2019

Dilution with Digital Microfluidic Biochips: How Unbalanced Splits Corrupt Target-Concentration.

[BibT_eX]

[DOI]

CoRR, 2019

Structural feature analysis of the vascular network in retinal images.

[BibT_eX]

[DOI]

Tapash Dutta

Nilanjan Dutta

Comput. methods Biomech. Biomed. Eng. Imaging Vis., 2019

Selective Sensitization of Useless Sneak-Paths for Test Optimization in Memristor-Arrays.

[BibT_eX]

[DOI]

Manobennath Mondal

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

Design of Continuous-Flow Lab-on-Chip with 3D Microfluidic Network for Sample Preparation.

[BibT_eX]

[DOI]

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

Flow-Based Passive Microfluidic Architecture for Homogeneous Mixing.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Embedded Computing and System Design, 2019

BioScan: Parameter-Space Exploration of Synthetic Biocircuits Using MEDA Biochips∗.

[BibT_eX]

[DOI]

Mohamed Ibrahim

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

A Prufer-Sequence Based Representation of Large Graphs for Structural Encoding of Logic Networks.

[BibT_eX]

[DOI]

Proceedings of the ACM India Joint International Conference on Data Science and Management of Data, 2019

Fault Coverage of a Test Set on Structure-Preserving Siblings of a Circuit-Under-Test.

[BibT_eX]

[DOI]

Manobendra Nath Mondal

Animesh Basak Chowdhury

Proceedings of the 28th IEEE Asian Test Symposium, 2019

Factorization based dilution of biochemical fluids with micro-electrode-dot-array biochips.

[BibT_eX]

[DOI]

Sohini Saha

Debraj Kundu

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Debugging Errors in Microfluidic Executions.

[BibT_eX]

[DOI]

Proceedings of the Advanced Computing and Systems for Security, 2019

Effect of Volumetric Split-Errors on Reactant-Concentration During Sample Preparation with Microfluidic Biochips.

[BibT_eX]

[DOI]

Proceedings of the Advanced Computing and Systems for Security, 2019

2018

Reliability-Aware Test Methodology for Detecting Short-Channel Faults in On-Chip Networks.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

Demand-Driven Single- and Multitarget Mixture Preparation Using Digital Microfluidic Biochips.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2018

Flexible Droplet Routing in Active Matrix-Based Digital Microfluidic Biochips.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2018

Concentration-Resilient Mixture Preparation with Digital Microfluidic Lab-on-Chip.

[BibT_eX]

[DOI]

Yi-Ling Chen

ACM Trans. Embed. Comput. Syst., 2018

Reliability Hardening Mechanisms in Cyber-Physical Digital-Microfluidic Biochips.

[BibT_eX]

[DOI]

Guan-Ruei Lu

ACM J. Emerg. Technol. Comput. Syst., 2018

Robust In-Field Testing of Digital Microfluidic Biochips.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2018

Test-Time Reduction for Power-Aware 3D-SoC.

[BibT_eX]

[DOI]

Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

ATPG Binning and SAT-Based Approach to Hardware Trojan Detection for Safety-Critical Systems.

[BibT_eX]

[DOI]

Animesh Basak Chowdhury

Proceedings of the Network and System Security - 12th International Conference, 2018

Detection of Osteoarthritis by Gap and Shape Analysis of Knee-Bone X-ray.

[BibT_eX]

[DOI]

Sabyasachi Mukherjee

Proceedings of the Combinatorial Image Analysis - 19th International Workshop, 2018

Test generation for microfluidic fully programmable valve arrays (FPVAs) with heuristic acceleration.

[BibT_eX]

[DOI]

Chunfeng Liu

Bing Li

Ulf Schlichtmann

Proceedings of the 2018 International Conference on IC Design & Technology, 2018

Storage-aware sample preparation using flow-based microfluidic Labs-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Multi-level droplet routing in active-matrix based digital-microfluidic biochips.

[BibT_eX]

[DOI]

Guan-Ruei Lu

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

COMEDI: Combinatorial Election of Diagnostic Vectors From Detection Test Sets for Logic Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Fast Estimation of Area-Coverage for Wireless Sensor Networks Based on Digital Geometry.

[BibT_eX]

[DOI]

Dibakar Saha

IEEE Trans. Multi Scale Comput. Syst., 2017

Dilution and Mixing Algorithms for Flow-Based Microfluidic Biochips.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Adaptation of Biochemical Protocols to Handle Technology-Change for Digital Microfluidics.

[BibT_eX]

[DOI]

Sharbatanu Chatterjee

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

On representing a simple polygon perceivable to a blind person.

[BibT_eX]

[DOI]

Sandip Banerjee

Inf. Process. Lett., 2017

A linear-time algorithm to compute the triangular hull of a digital object.

[BibT_eX]

[DOI]

Discret. Appl. Math., 2017

Does Rotation Influence the Estimated Contour Length of a Digital Object?

[BibT_eX]

[DOI]

Sabyasachi Mukherjee

Proceedings of the Pattern Recognition and Machine Intelligence, 2017

Testing microfluidic Fully Programmable Valve Arrays (FPVAs).

[BibT_eX]

[DOI]

Chunfeng Liu

Bing Li

Ulf Schlichtmann

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

On reliability hardening in cyber-physical digital-microfluidic biochips.

[BibT_eX]

[DOI]

Guan-Ruei Lu

Guan-Ming Huang

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Reservoir and mixer constrained scheduling for sample preparation on digital microfluidic biochips.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

Error-Correcting Sample Preparation with Cyberphysical Digital Microfluidic Lab-on-Chip.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2016

Thermal-Aware Small-Delay Defect Testing in Integrated Circuits for Mitigating Overkill.

[BibT_eX]

[DOI]

Kele Shen

Xiaoqing Wen

Xijiang Lin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Fault Diagnosis for Leakage and Blockage Defects in Flow-Based Microfluidic Biochips.

[BibT_eX]

[DOI]

Kai Hu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

On the Characterization of Absentee-Voxels in a Spherical Surface and Volume of Revolution in $ℤ^3.

[BibT_eX]

[DOI]

J. Math. Imaging Vis., 2016

Reversible Synthesis of Symmetric Functions with a Simple Regular Structure and Easy Testability.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2016

Automatic Segmentation of Bones in X-ray Images Based on Entropy Measure.

[BibT_eX]

[DOI]

Bhabatosh Chanda

Int. J. Image Graph., 2016

Simulation-based method for optimum microfluidic sample dilution using weighted mix-split of droplets.

[BibT_eX]

[DOI]

Nilina Bera

IET Comput. Digit. Tech., 2016

On Fault-Tolerant Design of Exclusive-OR Gates in QCA.

[BibT_eX]

[DOI]

Dharmendra Kumar

CoRR, 2016

Long-bone fracture detection in digital X-ray images based on digital-geometric techniques.

[BibT_eX]

[DOI]

Comput. Methods Programs Biomed., 2016

Power-aware test optimization for core-based 3D-SOCs under TSV-constraints.

[BibT_eX]

[DOI]

Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

On-line detection and diagnosis of stuck-at faults in channels of NoC-based systems.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Conference on Systems, Man, and Cybernetics, 2016

A topology-agnostic test model for link shorts in on-chip networks.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Conference on Systems, Man, and Cybernetics, 2016

One poison is antidote against another poison.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Conference on Systems, Man, and Cybernetics, 2016

Detecting and diagnosing open faults in NoC channels on activation of diagonal nodes.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Conference on Systems, Man, and Cybernetics, 2016

On the Inadmissible Class of Multiple-Valued Faulty-Functions under Stuck-at Faults.

[BibT_eX]

[DOI]

Debabani Chowdhury

Tsutomu Sasao

Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016

High-speed decoder design using memristor-based nano-crossbar architecture.

[BibT_eX]

[DOI]

Malay Kule

Avik Dutta

Proceedings of the Sixth International Symposium on Embedded Computing and System Design, 2016

Design automation of multiple-demand mixture preparation using a K-array rotary mixer on digital microfluidic biochips.

[BibT_eX]

[DOI]

Satendra Kumar

Ankur Gupta

Proceedings of the 34th IEEE International Conference on Computer Design, 2016

2015

Offline Washing Schemes for Residue Removal in Digital Microfluidic Biochips.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2015

Layout-Aware Mixture Preparation of Biochemical Fluids on Application-Specific Digital Microfluidic Biochips.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2015

Design and Optimization of a Cyberphysical Digital-Microfluidic Biochip for the Polymerase Chain Reaction.

[BibT_eX]

[DOI]

Yan Luo

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Waste-aware single-target dilution of a biochemical fluid using digital microfluidic biochips.

[BibT_eX]

[DOI]

Integr., 2015

A Fast and Automated Granulometric Image Analysis Based on Digital Geometry.

[BibT_eX]

[DOI]

Fundam. Informaticae, 2015

Guest Editors' Introduction: Microfluidics: Design and Test Solutions for Enabling Biochemistry on a Chip.

[BibT_eX]

[DOI]

IEEE Des. Test, 2015

On finding a shortest isothetic path and its monotonicity inside a digital object.

[BibT_eX]

[DOI]

Ann. Math. Artif. Intell., 2015

Fault diagnosis for flow-based microfluidic biochips.

[BibT_eX]

[DOI]

Kai Hu

Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Enumeration of Shortest Isothetic Paths Inside a Digital Object.

[BibT_eX]

[DOI]

Proceedings of the Pattern Recognition and Machine Intelligence, 2015

Design-for-testability in reversible logic circuits based on bit-swapping.

[BibT_eX]

[DOI]

Joyati Mondal

Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014

On-Chip Sample Preparation for Multiple Targets Using Digital Microfluidics.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

On the Suitability of Single-Walled Carbon Nanotube Bundle Interconnects for High-Speed and Power-Efficient Applications.

[BibT_eX]

[DOI]

Manodipan Sahoo

J. Low Power Electron., 2014

An Optimal Two-Mixer Dilution Engine with Digital Microfluidics for Low-Power Applications.

[BibT_eX]

[DOI]

J. Low Power Electron., 2014

Theory and analysis of generalized mixing and dilution of biochemical fluids using digital microfluidic biochips.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2014

High-throughput dilution engine for sample preparation on digital microfluidic biochips.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2014

Sample preparation with multiple dilutions on digital microfluidic biochips.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2014

On the family of shortest isothetic paths in a digital object - An algorithm with applications.

[BibT_eX]

[DOI]

Comput. Vis. Image Underst., 2014

On Chord and Sagitta in Z2: An Analysis towards Fast and Robust Circular Arc Detection.

[BibT_eX]

[DOI]

CoRR, 2014

On Covering a Solid Sphere with Concentric Spheres in ${\mathbb Z}^3$.

[BibT_eX]

[DOI]

CoRR, 2014

Correctness Checking of Bio-chemical Protocol Realizations on a Digital Microfluidic Biochip.

[BibT_eX]

[DOI]

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

A Fast Digital-Geometric Approach for Granulometric Image Analysis.

[BibT_eX]

[DOI]

Proceedings of the Recent Advances in Information Technology, 2014

A Combinatorial Technique for Construction of Triangular Covers of Digital Objects.

[BibT_eX]

[DOI]

Proceedings of the Combinatorial Image Analysis - 16th International Workshop, 2014

Long-Bone Fracture Detection in Digital X-ray Images Based on Concavity Index.

[BibT_eX]

[DOI]

Proceedings of the Combinatorial Image Analysis - 16th International Workshop, 2014

On Designing Robust Path-Delay Fault Testable Combinational Circuits Based on Functional Properties.

[BibT_eX]

[DOI]

Rupali Mitra

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

A Graph-Based 3D IC Partitioning Technique.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Inadmissible Class of Boolean Functions under Stuck-at Faults.

[BibT_eX]

[DOI]

Debabani Chowdhury

Tsutomu Sasao

Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014

Synthesis of Symmetric Boolean Functions Using a Three-Stage Network.

[BibT_eX]

[DOI]

Arighna Deb

Proceedings of the 2014 Fifth International Symposium on Electronic System Design, 2014

Design automation for biochemistry synthesis on a digital microfluidic lab-on-a-chip.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Algorithmic Challenges in Digital Microfluidic Biochips: Protocols, Design, and Test.

[BibT_eX]

[DOI]

Proceedings of the Applied Algorithms - First International Conference, 2014

Analysis of Concentration Errors in Sample Dilution Algorithms on a Digital Microfluidic Biochip.

[BibT_eX]

[DOI]

Nilina Bera

Proceedings of the Applied Algorithms - First International Conference, 2014

A Digital-Geometric Algorithm for Generating a Complete Spherical Surface in ℤ3.

[BibT_eX]

[DOI]

Proceedings of the Applied Algorithms - First International Conference, 2014

Demand-Driven Mixture Preparation and Droplet Streaming using Digital Microfluidic Biochips.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013

On covering a digital disc with concentric circles in Z2.

[BibT_eX]

[DOI]

Peer Stelldinger

Theor. Comput. Sci., 2013

On the Construction of Generalized Voronoi Inverse of a Rectangular Tessellation.

[BibT_eX]

[DOI]

Sandip Banerjee

Trans. Comput. Sci., 2013

A combinatorial algorithm to construct 3D isothetic covers.

[BibT_eX]

[DOI]

Nilanjana Karmakar

Int. J. Comput. Math., 2013

Algorithms for Producing Linear Dilution Gradient with Digital Microfluidics.

[BibT_eX]

[DOI]

CoRR, 2013

Derivation of test set for detecting multiple missing-gate faults in reversible circuits.

[BibT_eX]

[DOI]

Comput. Electr. Eng., 2013

On-Chip Dilution from Multiple Concentrations of a Sample Fluid Using Digital Microfluidics.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design and Test, 17th International Symposium, 2013

On Designing Testable Reversible Circuits Using Gate Duplication.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design and Test, 17th International Symposium, 2013

Reversible Circuit Synthesis of Symmetric Functions Using a Simple Regular Structure.

[BibT_eX]

[DOI]

Arighna Deb

Rolf Drechsler

Proceedings of the Reversible Computation - 5th International Conference, 2013

Bone Contour Tracing in Digital X-ray Images Based on Adaptive Thresholding.

[BibT_eX]

[DOI]

Bhabatosh Chanda

Proceedings of the Pattern Recognition and Machine Intelligence, 2013

Routing-aware resource allocation for mixture preparation in digital microfluidic biochips.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Impact of Inductance on the Performance of Single Walled Carbon Nanotube Bundle Interconnects.

[BibT_eX]

[DOI]

Manodipan Sahoo

Proceedings of the 2013 International Symposium on Electronic System Design, 2013

On Producing Linear Dilution Gradient of a Sample with a Digital Microfluidic Biochip.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Symposium on Electronic System Design, 2013

Optimal Two-Mixer Scheduling in Dilution Engine on a Digital Microfluidic Biochip.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Symposium on Electronic System Design, 2013

Optimization of polymerase chain reaction on a cyberphysical digital microfluidic biochip.

[BibT_eX]

[DOI]

Yan Luo

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Reversible synthesis of symmetric boolean functions based on unate decomposition.

[BibT_eX]

[DOI]

Arighna Deb

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Efficient mixture preparation on digital microfluidic biochips.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

2012

Congestion-aware layout design for high-throughput digital microfluidic biochips.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2012

A linear-time combinatorial algorithm to find the orthogonal hull of an object on the digital plane.

[BibT_eX]

[DOI]

Moumita Sarkar

Inf. Sci., 2012

Testing of Low-cost Digital Microfluidic Biochips with Non-Regular Array Layouts.

[BibT_eX]

[DOI]

Yang Zhao

J. Electron. Test., 2012

A heuristic method for obstacle avoiding group Steiner tree construction.

[BibT_eX]

[DOI]

Tuhina Samanta

Raka Sardar

Proceedings of the International Workshop on System Level Interconnect Prediction, 2012

On Finding Shortest Isothetic Path inside a Digital Object.

[BibT_eX]

[DOI]

Proceedings of the Combinatorial Image Analysis - 15th International Workshop, 2012

Algorithms for On-Chip Solution Preparation Using Digital Microfluidic Biochips.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

On-Chip Sample Preparation with Multiple Dilutions Using Digital Microfluidics.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Reversible Logic Circuit Synthesis Using Genetic Algorithm and Particle Swarm Optimization.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Electronic System Design, 2012

Multiple Dilution Sample Preparation Using Digital Microfluidic Biochips.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Electronic System Design, 2012

Low-Cost Dilution Engine for Sample Preparation in Digital Microfluidic Biochips.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Electronic System Design, 2012

Circularity analysis of nano-scale structures in porous silicon images.

[BibT_eX]

[DOI]

Nil R. Bandyopadhyay

Proceedings of the Computational Modelling of Objects Represented in Images, 2012

Automated path planning for washing in digital microfluidic biochips.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Conference on Automation Science and Engineering, 2012

A New Look Ahead Technique for Customized Testing in Digital Microfluidic Biochips.

[BibT_eX]

[DOI]

Pranab Roy

Proceedings of the 21st IEEE Asian Test Symposium, 2012

On-Line Error Detection in Digital Microfluidic Biochips.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011

A Routing-Aware ILS Design Technique.

[BibT_eX]

[DOI]

Jimson Mathew

Dhiraj K. Pradhan

Saraju P. Mohanty

IEEE Trans. Very Large Scale Integr. Syst., 2011

On the representation of a digital contour with an unordered point set for visual perception.

[BibT_eX]

[DOI]

J. Vis. Commun. Image Represent., 2011

On finding an orthogonal convex skull of a digital object.

[BibT_eX]

[DOI]

Int. J. Imaging Syst. Technol., 2011

Efficient Word Segmentation and Baseline Localization in Handwritten Documents Using Isothetic Covers.

[BibT_eX]

[DOI]

Int. J. Digit. Libr. Syst., 2011

Test Planning in Digital Microfluidic Biochips Using Efficient Eulerization Techniques.

[BibT_eX]

[DOI]

J. Electron. Test., 2011

Fault diagnosis in reversible circuits under missing-gate fault model.

[BibT_eX]

[DOI]

Comput. Electr. Eng., 2011

Layout-Aware Solution Preparation for Biochemical Analysis on a Digital Microfluidic Biochip.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

Entropy-Based Automatic Segmentation of Bones in Digital X-ray Images.

[BibT_eX]

[DOI]

Bhabatosh Chanda

Proceedings of the Pattern Recognition and Machine Intelligence, 2011

Construction of 3D Orthogonal Cover of a Digital Object.

[BibT_eX]

[DOI]

Nilanjana Karmakar

Proceedings of the Combinatorial Image Analysis - 14th International Workshop, 2011

Derivation of Automatic Test Set for Detection of Missing Gate Faults in Reversible Circuits.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Electronic System Design, 2011

On residue removal in digital microfluidic biochips.

[BibT_eX]

[DOI]

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Waste-aware dilution and mixing of biochemical samples with digital microfluidic biochips.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

Diagnosis of Multiple Scan-Chain Faults in the Presence of System Logic Defects.

[BibT_eX]

[DOI]

Zhen Chen

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010

Optimization of Dilution and Mixing of Biochemical Samples Using Digital Microfluidic Biochips.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Construction of isothetic covers of a digital object: A combinatorial approach.

[BibT_eX]

[DOI]

J. Vis. Commun. Image Represent., 2010

PVT: Unified Reduction of Test Power, Volume, and Test Time Using Double-Tree Scan Architecture.

[BibT_eX]

[DOI]

Zhen Chen

J. Low Power Electron., 2010

Recognition of largest empty orthoconvex polygon in a point set.

[BibT_eX]

[DOI]

Krishnendu Mukhopadhyaya

Inf. Process. Lett., 2010

Understanding Digital Documents Using Gestalt Properties of Isothetic Components.

[BibT_eX]

[DOI]

Int. J. Digit. Libr. Syst., 2010

Test pattern generation for droop faults.

[BibT_eX]

[DOI]

Sandip Kundu

Ashish Nigam

Sandeep K. Dey

IET Comput. Digit. Tech., 2010

Separating Multi-Color Points on a Plane with Fewest Axis-Parallel Lines.

[BibT_eX]

[DOI]

Fundam. Informaticae, 2010

A Simple Algorithm for Approximate Partial Point Set Pattern Matching under Rigid Motion.

[BibT_eX]

[DOI]

Proceedings of the WALCOM: Algorithms and Computation, 4th International Workshop, 2010

A Unified Solution to Scan Test Volume, Time, and Power Minimization.

[BibT_eX]

[DOI]

Zhen Chen

Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

A BDD-based approach to design power-aware on-line detectors for digital circuits.

[BibT_eX]

[DOI]

Chittaranjan A. Mandal

Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

A BDD-Based Design of an Area-Power Efficient Asynchronous Adder.

[BibT_eX]

[DOI]

Rohit Reddy

Chittaranjan A. Mandal

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Word Segmentation and Baseline Detection in Handwritten Documents Using Isothetic Covers.

[BibT_eX]

[DOI]

Aisharjya Sarkar

Proceedings of the International Conference on Frontiers in Handwriting Recognition, 2010

Recognition of Hand-Drawn Graphs Using Digital-Geometric Techniques.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Frontiers in Handwriting Recognition, 2010

Testing of Digital Microfluidic Biochips Using Improved Eulerization Techniques and the Chinese Postman Problem.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE Asian Test Symposium, 2010

Derivation of Optimal Test Set for Detection of Multiple Missing-Gate Faults in Reversible Circuits.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009

Removal of digitization errors in fingerprint ridgelines using B-splines.

[BibT_eX]

[DOI]

Pattern Recognit., 2009

Approximate Matching of Digital Point Sets Using a Novel Angular Tree.

[BibT_eX]

[DOI]

Ranjan K. Pradhan

IEEE Trans. Pattern Anal. Mach. Intell., 2009

Droop sensitivity of stuck-at fault tests.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2009

Real Polygonal Covers of Digital Discs - Some Theories and Experiments.

[BibT_eX]

[DOI]

Fundam. Informaticae, 2009

Testable design of AND-EXOR logic networks with universal test sets.

[BibT_eX]

[DOI]

Comput. Electr. Eng., 2009

Algorithms for Biological Cell Sorting with a Lab-on-a-chip.

[BibT_eX]

[DOI]

Arijit Ghosh

Rushin Shah

Proceedings of the World Congress on Nature & Biologically Inspired Computing, 2009

On Finding the Orthogonal Convex Skull of a Digital Object.

[BibT_eX]

Proceedings of the Progress in Combinatorial Image Analysis. Proceedings of IWCIA 2009 Special Track on Applications, 2009

Digital Circularity and Its Applications.

[BibT_eX]

[DOI]

Proceedings of the Combinatorial Image Analysis, 13th International Workshop, 2009

GOAL: Towards Understanding of Graphic Objects from Architectural to Line Drawings.

[BibT_eX]

[DOI]

Proceedings of the Graphics Recognition. Achievements, 2009

Detection of Circular Arcs in a Digital Image Using Chord and Sagitta Properties.

[BibT_eX]

[DOI]

Proceedings of the Graphics Recognition. Achievements, 2009

2008

An Adaptive BIST Design for Detecting Multiple Stuck-Open Faults in a CMOS Complex Cell.

[BibT_eX]

[DOI]

IEEE Trans. Instrum. Meas., 2008

On the density and discrepancy of a 2D point set with applications to thermal analysis of VLSI chips.

[BibT_eX]

[DOI]

Inf. Process. Lett., 2008

Planar Straight-Line Embedding of Double-Tree Scan Architecture on a Rectangular Grid.

[BibT_eX]

[DOI]

Indranil Saha

Fundam. Informaticae, 2008

A New Probabilistic Approach for Fractal Based Image Compression.

[BibT_eX]

[DOI]

Suman K. Mitra

Fundam. Informaticae, 2008

Number-theoretic interpretation and construction of a digital circle.

[BibT_eX]

[DOI]

Discret. Appl. Math., 2008

Archival image indexing with connectivity features using randomized masks.

[BibT_eX]

[DOI]

Appl. Soft Comput., 2008

On the Detection of Missing-Gate Faults in Reversible Circuits by a Universal Test Set.

[BibT_eX]

[DOI]

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Finding the Orthogonal Hull of a Digital Object: A Combinatorial Approach.

[BibT_eX]

[DOI]

Moumita Sarkar

Proceedings of the Combinatorial Image Analysis, 12th International Workshop, 2008

Digital Microfluidic Biochips: Design and Testing.

[BibT_eX]

[DOI]

Proceedings of the IEEE Reglon 10 Colloquium and Third International Conference on Industrial and Information Systems, 2008

Extraction of regions of interest from face images using cellular analysis.

[BibT_eX]

[DOI]

Suman Khara

Proceedings of the 1st Bangalore Annual Compute Conference, Compute 2008, 2008

Accelerated Functional Testing of Digital Microfluidic Biochips.

[BibT_eX]

[DOI]

D. Dutta Majumder

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007

Hierarchical partitioning of VLSI floorplans by staircases.

[BibT_eX]

[DOI]

Swarup Kumar Das

ACM Trans. Design Autom. Electr. Syst., 2007

An Efficient Scan Tree Design for Compact Test Pattern Set.

[BibT_eX]

[DOI]

Dipanwita Roy Chowdhury

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Stacked Euler Vector (SERVE): A Gray-Tone Image Feature Based on Bit-Plane Augmentation.

[BibT_eX]

[DOI]

IEEE Trans. Pattern Anal. Mach. Intell., 2007

Fast Polygonal Approximation of Digital Curves Using Relaxed Straightness Properties.

[BibT_eX]

[DOI]

IEEE Trans. Pattern Anal. Mach. Intell., 2007

A Co-processor for Computing the Euler Number of a Binary Image using Divide-and-Conquer Strategy.

[BibT_eX]

[DOI]

Malay K. Kundu

Fundam. Informaticae, 2007

A Local Search Heuristic for Biobjective Intersecting Geometric Graphs.

[BibT_eX]

[DOI]

Rajeev Kumar

Pramod Kumar Singh

Proceedings of the 2007 International Conference on Computing: Theory and Applications (ICCTA 2007), 2007

Characterization of Isothetic Polygons for Image Indexing and Retrieval.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computing: Theory and Applications (ICCTA 2007), 2007

Ranking of Optical Character Prototypes in a Large Database Using Isothetic Chord Lengths.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computing: Theory and Applications (ICCTA 2007), 2007

ICE: The Isothetic Convex Envelope of a Digital Object.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computing: Theory and Applications (ICCTA 2007), 2007

Optimum Test Set for Bridging Fault Detection in Reversible Circuits.

[BibT_eX]

[DOI]

Proceedings of the 16th Asian Test Symposium, 2007

2006

Simple algorithms for partial point set pattern matching under rigid motion.

[BibT_eX]

[DOI]

Pattern Recognit., 2006

Implementing Symmetric Functions with Hierarchical Modules for Stuck-At and Path-Delay Fault Testability.

[BibT_eX]

[DOI]

J. Electron. Test., 2006

Test Pattern Generation for Power Supply Droop Faults.

[BibT_eX]

[DOI]

Subhasis Bhattacharjee

Sujit T. Zachariah

Sandip Kundu

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Solving Thermal Problems of Hot Chips Using Voronoi Diagrams.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Recovery-Based Real-Time Static Scheduling for Battery Life Optimization.

[BibT_eX]

[DOI]

Anirban Lahiri

Saurabh Agarwal

Anupam Basu

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

PACE: Polygonal Approximation of Thick Digital Curves Using Cellular Envelope.

[BibT_eX]

[DOI]

Proceedings of the Computer Vision, Graphics and Image Processing, 5th Indian Conference, 2006

On finding the minimum test set of a BDD-based circuit.

[BibT_eX]

[DOI]

Ajit Pal

Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Biobjective evolutionary and heuristic algorithms for intersection of geometric graphs.

[BibT_eX]

[DOI]

Rajeev Kumar

Pramod Kumar Singh

Proceedings of the Genetic and Evolutionary Computation Conference, 2006

Low Power BDD-based Synthesis Using Dual Rail Static DCVSPG Logic.

[BibT_eX]

[DOI]

Sambhu Nath Pradhan

Ajit Pal

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005

Euler vector for search and retrieval of gray-tone images.

[BibT_eX]

[DOI]

IEEE Trans. Syst. Man Cybern. Part B, 2005

A pipeline architecture for computing the Euler number of a binary image.

[BibT_eX]

[DOI]

Malay K. Kundu

J. Syst. Archit., 2005

Determination of Minutiae Scores for Fingerprint Image Applications.

[BibT_eX]

[DOI]

Int. J. Image Graph., 2005

On Finding Consecutive Test Vectors in a Random Sequence for Energy-Aware BIST Design.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Hot Spots and Zones in a Chip: A Geometrician's View.

[BibT_eX]

[DOI]

B. Chakraborty

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

TIPS: On Finding a Tight Isothetic Polygonal Shape Covering a 2D Object.

[BibT_eX]

[DOI]

Proceedings of the Image Analysis, 14th Scandinavian Conference, 2005

A Hybrid Data and Space Partitioning Technique for Similarity Queries on Bounded Clusters.

[BibT_eX]

[DOI]

Piyush Kanti Bhunre

Proceedings of the Pattern Recognition and Machine Intelligence, 2005

Isothetic Polygonal Approximations of a 2D Object on Generalized Grid.

[BibT_eX]

[DOI]

Proceedings of the Pattern Recognition and Machine Intelligence, 2005

A programmable built-in self-test for embedded DRAMs.

[BibT_eX]

[DOI]

Dipanwita Roy Chowdhury

Proceedings of the 13th IEEE International Workshop on Memory Technology, 2005

Reconstruction of torn documents using contour maps.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Image Processing, 2005

Approximation of Digital Circles by Regular Polygons.

[BibT_eX]

[DOI]

Proceedings of the Pattern Recognition and Data Mining, 2005

MUSC: Multigrid Shape Codes and Their Applications to Image Retrieval.

[BibT_eX]

[DOI]

Proceedings of the Computational Intelligence and Security, International Conference, 2005

Density or Discrepancy: A VLSI Designer's Dilemma in Hot Spot Analysis.

[BibT_eX]

[DOI]

Proceedings of the 17th Canadian Conference on Computational Geometry, 2005

Efficient Test Compaction for Pseudo-Random Testing.

[BibT_eX]

[DOI]

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

CryptoScan: A Secured Scan Chain Architecture.

[BibT_eX]

[DOI]

Debdeep Mukhopadhyay

Dipanwita Roy Chowdhury

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

Manhattan-diagonal routing in channels and switchboxes.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2004

A New Classification of Path-Delay Fault Testability in Terms of Stuck-at Faults.

[BibT_eX]

[DOI]

Vishwani D. Agrawal

Michael L. Bushnell

J. Comput. Sci. Technol., 2004

On Finding A Staircase Channel With Minimum Crossing Nets In A VLSI Floorplan.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2004

Physical Design Trends and Layout-Based Fault Modeling.

[BibT_eX]

[DOI]

Sujit T. Zachariah

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Easily Testable Realization of GRM and ESOP Networks for Detecting Stuck-at and Bridging Faults.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

CONFERM: Connectivity Features with Randomized Masks and Their Applications to Image Indexing.

[BibT_eX]

Proceedings of the ICVGIP 2004, 2004

CODE: An Adaptive Algorithm for Detecting Corners and Directions of Incident Edges.

[BibT_eX]

Proceedings of the ICVGIP 2004, 2004

Approximate Fingerprint Matching Using Kd-Tree.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on Pattern Recognition, 2004

Testable design of GRM network with EXOR-tree for detecting stuck-at and bridging faults.

[BibT_eX]

[DOI]

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

Zero-Aliasing Space Compaction of Test Responses Using a Single Periodic Output.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2003

Permutation routing in optical MIN with minimum number of stages.

[BibT_eX]

[DOI]

Sergei L. Bezrukov

J. Syst. Archit., 2003

On finding an empty staircase polygon of largest area (width) in a planar point-set.

[BibT_eX]

[DOI]

Comput. Geom., 2003

Low-Energy BIST Design for Scan-based Logic Circuits.

[BibT_eX]

[DOI]

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Double-Tree Scan: A Novel Low-Power Scan-Path Architecture.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

An Improved Algorithm for Point Set Pattern Matching under Rigid Motion.

[BibT_eX]

[DOI]

Proceedings of the Algorithms and Complexity, 5th Italian Conference, 2003

Mapping Symmetric Functions to Hierarchical Modules for Path-Delay Fault Testability.

[BibT_eX]

[DOI]

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002

Monotone bipartitioning problem in a planar point set with applications to VLSI.

[BibT_eX]

[DOI]

Peichen Pan

ACM Trans. Design Autom. Electr. Syst., 2002

Synthesis of single-output space compactors for scan-based sequential circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

BIST Design for Detecting Multiple Stuck-Open Faults in CMOS Circuits Using Transition Count.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2002

A Simple Architecture for Computing Moments and Orientation of an Image.

[BibT_eX]

[DOI]

Fundam. Informaticae, 2002

A New Synthesis of Symmetric Functions.

[BibT_eX]

[DOI]

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Euler Vector: A Combinatorial Signature for Gray-Tone Images.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Information Technology (ITCC 2002), 2002

Combinatorial Classification of Pixels for Ridge Extraction in a Gray-Scale Fingerprint Image.

[BibT_eX]

Proceedings of the ICVGIP 2002, 2002

Content based image retrieval: related issues using Euler vector.

[BibT_eX]

[DOI]

Swarup Bhunia

Proceedings of the 2002 International Conference on Image Processing, 2002

2001

Searching networks with unrestricted edge costs.

[BibT_eX]

[DOI]

Anup K. Sen

IEEE Trans. Syst. Man Cybern. Part A, 2001

Design of Parameterizable Error-Propagating Space Compactors for Response Observation.

[BibT_eX]

[DOI]

Andrej A. Morosov

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Partitioning Routing Area into Zones with Distinct Pins.

[BibT_eX]

[DOI]

Koushik Sinha

P. S. Dasgupta

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Testable Design of Sequential Circuits with Improved Fault Efficiency.

[BibT_eX]

[DOI]

Satoshi Ohtake

Hideo Fujiwara

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Fractal Image Compression Using Iterated Function System with Probabilities.

[BibT_eX]

[DOI]

Suman K. Mitra

Proceedings of the 2001 International Symposium on Information Technology (ITCC 2001), 2001

Area(number)-balanced hierarchy of staircase channels with minimum crossing nets.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

On-chip computation of Euler number of a binary image for efficient database search.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Conference on Image Processing, 2001

Synthesis of single-output space compactors with application to scan-based IP cores.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2001, 2001

2000

Synthesis of symmetric functions for path-delay fault testability.

[BibT_eX]

[DOI]

Susanta Chakrabarti

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Isomorph-Redundancy in Sequential Circuits.

[BibT_eX]

[DOI]

Uttam K. Bhattacharya

IEEE Trans. Computers, 2000

Safety Zone Problem.

[BibT_eX]

[DOI]

Antonio Hernández-Barrera

J. Algorithms, 2000

A Fast Algorithm for Computing the Euler Number of an Image and its VLSI Implementation.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Topological Routing Amidst Polygonal Obstacles.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Zero-Aliasing Space Compression using a Single Periodic Output and its Application to Testing of Embedded Cores.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

1999

A Complete Characterization of Path Delay Faults through Stuck-at Faults.

[BibT_eX]

[DOI]

Vishwani D. Agrawal

Michael L. Bushnell

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

High Performance MCM Routing: A New Approach.

[BibT_eX]

[DOI]

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Synthesis of Symmetric Functions for Path-Delay Fault Testability.

[BibT_eX]

[DOI]

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

An Adaptive BIST to Detect Multiple Stuck-Open Faults in CMOS circuits.

[BibT_eX]

[DOI]

Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1998

A unified approach to topology generation and optimal sizing of floorplans.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Partitioning VLSI Floorplans by Staircase Channels for Global Routing.

[BibT_eX]

[DOI]

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Routing of L-Shaped Channels, Switchboxes and Staircases in Manhattan-Diagonal Model.

[BibT_eX]

[DOI]

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Design of an Optimal Test Pattern Generator for Built-in Self Testing of Path Delay Faults.

[BibT_eX]

[DOI]

Indrajit Chaudhuri

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Permutation admissibility in shuffle-exchange networks with arbitrary number of stages.

[BibT_eX]

[DOI]

Rekha Menon

Sergei L. Bezrukov

Proceedings of the 5th International Conference On High Performance Computing, 1998

Interchangeable Boolean Functions and Their Effects on Redundancy in Logic Circuits.

[BibT_eX]

[DOI]

Proceedings of the ASP-DAC '98, 1998

1997

New BIST Techniques for Universal and Robust Testing of CMOS Stuck-Open Faults.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

1996

A Methodology for Testing Arbitrary Bilateral Bit-Level Systolic Arrays.

[BibT_eX]

[DOI]

Subir Bandyopadhyay

Abhijit Sengupta

VLSI Design, 1996

Geometric bipartitioning problem and its applications to VLSI.

[BibT_eX]

[DOI]

Anup K. Sen

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Does retiming affect redundancy in sequential circuits?

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Channel routing in Manhattan-diagonal model.

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Shooter Location Problem.

[BibT_eX]

[DOI]

Krishnendu Mukhopadhyaya

Proceedings of the 8th Canadian Conference on Computational Geometry, 1996

1995

VLSI floorplan generation and area optimization using AND-OR graph search.

[BibT_eX]

[DOI]

P. S. Dasgupta

Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

A unified approach to topology generation and area optimization of general floorplans.

[BibT_eX]

[DOI]

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Testable design of non-scan sequential circuits using extra logic.

[BibT_eX]

[DOI]

Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

1994

Hierarchical Classification of Permutation Classes in Multistage Interconnection Networks.

[BibT_eX]

[DOI]

Jayasree Dattagupta

IEEE Trans. Computers, 1994

Location of the Largest Empty Rectangle among Arbitrary Obstacles.

[BibT_eX]

[DOI]

Arani Sinha

Proceedings of the Foundations of Software Technology and Theoretical Computer Science, 1994

1993

Isomorphism of Conflict Graphs in Multistage Interconnection Networks and Its Application to Optimal Routing.

[BibT_eX]

[DOI]

Jayasree Dattagupta

IEEE Trans. Computers, 1993

Logical redundancies in irredundant combinational circuits.

[BibT_eX]

[DOI]

J. Electron. Test., 1993

Via Minimization in Channel Routing by Layout Modification.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Conference on VLSI Design, 1993

1992

Canonical Embedding of Rectangular Duals with Applications to VLSI Floorplanning.

[BibT_eX]

[DOI]

Proceedings of the 29th Design Automation Conference, 1992

1991

On the Testable Design of Bilateral Bit-Level Systolic Arrays.

[BibT_eX]

[DOI]

Subir Bandyopadhyay

Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

The Cycle Structure of Channel Graphs in Nonslicible Floorplans and A Unified Algorithm for Feasible Routing Order.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

1990

Efficient algorithms for Identifying All Maximal Isothetic Empty Rectangles in VLSI Layout Design.

[BibT_eX]

[DOI]

Sibabrata Ray

Proceedings of the Foundations of Software Technology and Theoretical Computer Science, 1990

1989

Via minimization in VLSI routing with movable terminals.

[BibT_eX]

[DOI]

Jitender S. Deogun

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

Design of Parity Testable Combinational Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1989

1988

A fast fault simulation algorithm for combinational circuits.

[BibT_eX]

[DOI]

Wuudiann Ke

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

Inherent Nonslicibility of Rectangular Duals in VLSI Floorplanning.

[BibT_eX]

[DOI]

Proceedings of the Foundations of Software Technology and Theoretical Computer Science, 1988

1986

A Parallel Algorithm to Compute the Shortest Paths and Diameter of a Graph and Its VLSI Implementation.

[BibT_eX]

[DOI]

Bhabani P. Sinha

Suranjan Ghose

Pradip K. Srimani

IEEE Trans. Computers, 1986

On the Impossible Class of Faulty Functions in Logic Networks Under Short Circuit Faults.

[BibT_eX]

[DOI]

Bidyut Gupta

IEEE Trans. Computers, 1986

1985

On the Numerical Complexity of Short-Circuit Faults in Logic Networks.

[BibT_eX]

[DOI]

Bhabani P. Sinha

IEEE Trans. Computers, 1985

1984

Logical Modeling of Physical Failures and Their Inherent Syndrome Testability in MOS LSI/VLSI Networks.

[BibT_eX]

Bidyut Gupta

Proceedings of the Proceedings International Test Conference 1984, 1984

Heuristic Search Approach to Optimal Routing in a Distributed Architecture.

[BibT_eX]

[DOI]

Suranjan Ghose

Bhabani P. Sinha

Pradip K. Srimani

Proceedings of the Foundations of Software Technology and Theoretical Computer Science, 1984

1983

Syndrome Testable Design of Combinational Networks for Detecting Stuck-At and Bridging Faults.

[BibT_eX]