Biswajit Patra

Orcid: 0009-0001-3001-1769

According to our database1, Biswajit Patra authored at least 8 papers between 2011 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Does digital payment induce economic growth in emerging economies? The mediating role of institutional quality, consumption expenditure, and bank credit.
Inf. Technol. Dev., January, 2024

2023
Precise and Faster Image Description Generation with Limited Resources Using an Improved Hybrid Deep Model.
Proceedings of the Pattern Recognition and Machine Intelligence, 2023

2020
8.1 Lakefield and Mobility Compute: A 3D Stacked 10nm and 22FFL Hybrid Processor System in 12×12mm<sup>2</sup>, 1mm Package-on-Package.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2017
Usability, tested?
Interactions, 2017

2015
A framework for energy efficient and flexible offloading scheme for handheld devices.
Proceedings of the 2015 IEEE International Conference on Advanced Networks and Telecommuncations Systems, 2015

2014
Post Optimization of a Clock Tree for Dynamic Clock Tree Power Reduction in 45 nm and Below Technology Nodes.
J. Low Power Electron., 2014

2012
A Novel Approach to Voltage-Drop Aware Placement in Large SoCs in Advanced Technology Nodes.
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

2011
An Efficient Methodology for Full Chip Signal ElectroMigration Analysis for Advanced Technology Node Designs.
J. Low Power Electron., 2011


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