Bo Liu

According to our database, Bo Liu authored at least 23 papers between 2010 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Response surface methodology based synchronous multi-performance optimization of CMOS low-dropout regulator.

Bo Liu, Pengfei Wang, Xiang Liu, Liwen Zhang

Microelectron. J., January, 2024

2023

BP Neural Network Modeling and Solving Acceleration of Analog ICs.

Bo Liu, Weizhe Zhang, Wenjuan Duan, Qingduan Meng

Circuits Syst. Signal Process., December, 2023

High-Efficiency Multiobjective Synchronous Modeling and Solution of Analog ICs.

Bo Liu, Weizhe Zhang, Kai Li, Wenjuan Duan, Min Liu, Qingduan Meng

Circuits Syst. Signal Process., April, 2023

Adaptive particle swarm optimization based hybrid small-signal modeling of GaN HEMT.

Haiyi Cai, Jincan Zhang, Min Liu, Shi Yang, Shaowei Wang, Bo Liu, Juwei Zhang

Microelectron. J., 2023

2022

IACRA: Lifetime Optimization by Invulnerability-Aware Clustering Routing Algorithm Using Game-Theoretic Approach for Wsns.

Jun Wang, Yadan Zhang, Chunyan Hu, Pengjun Mao, Bo Liu

Sensors, 2022

Hybrid small-signal modeling of GaN HEMTs based on improved genetic algorithm.

Jincan Zhang, Xuefeng Hou, Min Liu, Shi Yang, Bo Liu, Jinchan Wang, Juwei Zhang

Microelectron. J., 2022

A precision programmable multilevel voltage output and low-temperature-variation CMOS bandgap reference with area-efficient transistor-array layout.

Bo Liu, Pengfei Wang, Kai Li, Binrui Xu, Jincan Zhang, Liwen Zhang

Integr., 2022

Large-Signal Behavior Modeling of GaN P-HEMT Based on GA-ELM Neural Network.

Shaowei Wang, Jincan Zhang, Min Liu, Bo Liu, Jinchan Wang, Shi Yang

Circuits Syst. Signal Process., 2022

2021

An improved GaN P-HEMT small-signal equivalent circuit with its parameter extraction.

Jincan Zhang, Shaowei Wang, Min Liu, Bo Liu, Jinchan Wang

Microelectron. J., 2021

2019

Design of a Low-Phase-Noise Ka-Band GaAs HBT VCO.

Jincan Zhang, Min Liu, Liwen Zhang, Jinchan Wang, Bo Liu

J. Circuits Syst. Comput., 2019

Density Optimization for Analog Layout Based on Transistor-Array.

Chao Geng, Bo Liu, Shigetoshi Nakatake

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019

2018

Routable and Matched Layout Styles for Analog Module Generation.

Bo Liu, Gong Chen, Bo Yang, Shigetoshi Nakatake

ACM Trans. Design Autom. Electr. Syst., 2018

2017

Analog Characterization Module with Data Converter-Coupled Signal Reconfiguration.

Daishi Isogai, Bo Liu, Yoritaka Ishiguchi, Shigetoshi Nakatake

Proceedings of the New Generation of CAS, 2017

Explicit layout pattern density controlling based on transistor-array-style.

Chao Geng, Bo Liu, Shigetoshi Nakatake

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Low Voltage Stochastic Flash ADC with Front-end of Inverter-based Comparative Unit.

Xuncheng Zou, Bo Liu, Shigetoshi Nakatake

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

2016

A <i>Ku</i>-Band Low-Phase-Noise Cross-Coupled VCO in GaAs HBT Technology.

Jincan Zhang, Yuming Zhang, Hongliang Lu, Yimen Zhang, Bo Liu, Leiming Zhang, Jinchan Wang, Liwen Zhang

J. Circuits Syst. Comput., 2016

A multi-functional memory unit with PLA-based reconfigurable decoder.

Nobuyuki Yahiro, Bo Liu, Atsushi Nanri, Shigetoshi Nakatake, Yasuhiro Takashima, Gong Chen

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

Routability of twisted common-centroid capacitor array under signal coupling constraints.

Gong Chen, Bo Liu, Shigetoshi Nakatake, Bo Yang

Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

Twin-row-style for MOS analog layout.

Bo Liu, Shigetoshi Nakatake, Bo Yang, Gong Chen

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2012

Layout-Aware Variability Characterization of CMOS Current Sources.

Bo Liu, Bo Yang, Shigetoshi Nakatake

IEICE Trans. Electron., 2012

CMOS op-amp circuit synthesis with geometric programming models for layout-dependent effects.

Yu Zhang, Bo Liu, Bo Yang, Jing Li, Shigetoshi Nakatake

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

2011

Layout-aware mismatch modeling for CMOS current sources with D/A converter analysis.

Bo Liu, Qing Dong, Bo Yang, Jing Li, Shigetoshi Nakatake

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

2010

D-A converter based variation analysis for analog layout design.

Bo Liu, Toru Fujimura, Bo Yang, Shigetoshi Nakatake

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010