Yasuhiro Takashima

According to our database, Yasuhiro Takashima authored at least 36 papers between 1996 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2021

Theoretical and Experimental Analysis of Traveling Salesman Walk Problem.

Yasuhiro Takashima, Yuichi Nakamura

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2021

2018

Task Allocation and Scheduling Optimization in the Heterogeneous Core System.

Ryota Tsuchihashi, Komei Nomura, Yasuhiro Takashima, Yuichi Nakamura

Proceedings of the 2018 New Generation of CAS, 2018

Fast Approximate Algorithm for the Single Source Shortest Path with Lazy Update.

Tomohiro Takahashi, Yasuhiro Takashima

Proceedings of the 2018 New Generation of CAS, 2018

2016

An Online Task Placement Algorithm Based on MER Enumeration for Partially Reconfigurable Device.

Tieyuan Pan, Li Zhu, Lian Zeng, Takahiro Watanabe, Yasuhiro Takashima

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

A Fast MER Enumeration Algorithm for Online Task Placement on Reconfigurable FPGAs.

Tieyuan Pan, Lian Zeng, Yasuhiro Takashima, Takahiro Watanabe

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

A multi-functional memory unit with PLA-based reconfigurable decoder.

Nobuyuki Yahiro, Bo Liu, Atsushi Nanri, Shigetoshi Nakatake, Yasuhiro Takashima, Gong Chen

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

PEVaS: Power and execution-time variation-aware scheduling for MPSoC.

Komei Nomura, Yasuhiro Takashima, Yuichi Nakamura

Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

7.7 A 768Gb 3b/cell 3D-floating-gate NAND flash memory.

Tomoharu Tanaka, Mark Helm, Tommaso Vali, Ramin Ghodsi, Koichi Kawai, Jae-Kwan Park, Shigekazu Yamada, Feng Pan, Yuichi Einaga, Ali Ghalam, Toru Tanzawa, Jason Guo, Takaaki Ichikawa, Erwin Yu, Satoru Tamada, Tetsuji Manabe, Jiro Kishimoto, Yoko Oikawa, Yasuhiro Takashima, Hidehiko Kuge, Midori Morooka, Ali Mohammadzadeh, Jong Kang, Jeff Tsai, Emanuele Sirizotti, Eric Lee, Luyen Vu, Yuxing Liu, Hoon Choi, Kwonsu Cheon, Daesik Song, Daniel Shin, Jung Hee Yun, Michele Piccardi, Kim-Fung Chan, Yogesh Luthra, Dheeraj Srinivasan, Srinivasarao Deshmukh, Kalyan Kavalipurapu, Dan Nguyen, Girolamo Gallo, Sumant Ramprasad, Michelle Luo, Qiang Tang, Michele Incarnati, Agostino Macerola, Luigi Pilolli, Luca De Santis, Massimo Rossini, Violante Moschiano, Giovanni Santin, Bernardino Tronca, Hyunseok Lee, Vipul Patel, Ted Pekny, Aaron Yip, Naveen Prabhu, Purval Sule, Trupti Bemalkhedkar, Kiranmayee Upadhyayula, Camila Jaramillo

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015

Inter-FPGA Routing for Partially Time-Multiplexing Inter-FPGA Signals on Multi-FPGA Systems with Various Topologies.

Masato Inagi, Yuichi Nakamura, Yasuhiro Takashima, Shin'ichi Wakabayashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

Analytical placement for rectilinear blocks.

Yasuhiro Takashima

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

A randomized algorithm for the fixed-length routing problem.

Tieyuan Pan, Ran Zhang, Yasuhiro Takashima, Takahiro Watanabe

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

Delay estimation method for correlated net delay variations.

Masatsugu Hosoki, Seiya Nagatsuka, Yasuhiro Takashima

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013

An Effective Overlap Removable Objective for Analytical Placement.

Syota Kuwabara, Yukihide Kohira, Yasuhiro Takashima

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

An acceleration method by GPGPU for analytical placement using quasi-Newton method.

Syota Kuwabara, Yukihide Kohira, Yasuhiro Takashima

Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012

Sub-path delay estimation for reconvergent path.

Seiya Nagatsuka, Yasuhiro Takashima

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2010

Globally Optimal Time-multiplexing of Inter-FPGA Connections for Multi-FPGA Prototyping Systems.

Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura

IPSJ Trans. Syst. LSI Des. Methodol., 2010

Delay analysis of sub-path on fabricated chips by several path-delay tests.

Takanobu Shiki, Yasuhiro Takashima, Yuichi Nakamura

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009

A 172mm² 32Gb MLC NAND flash memory in 34nm CMOS.

Raymond Zeng, Navneet Chalagalla, Dan Chu, Daniel Elmhurst, Matt Goldman, Chris Haid, Atif Huq, Takaaki Ichikawa, Joel Jorgensen, Owen Jungroth, Nishnat Kajla, Ravinder Kajley, Koichi Kawai, Jiro Kishimoto, Ali Madraswala, Tetsuji Manabe, Vikram Mehta, Midori Morooka, Katie Nguyen, Yoko Oikawa, Bharat Pathak, Rod Rozman, Tom Ryan, Andy Sendrowski, William Sheung, Martin Szwarc, Yasuhiro Takashima, Satoru Tamada, Toru Tanzawa, Tomoharu Tanaka, Mase Taub, Darshak Udeshi, Sjigekazu Yamada, Hiroyuki Yokoyama

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

Globally optimal time-multiplexing in inter-FPGA connections for accelerating multi-FPGA systems.

Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura

Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

2008

Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems.

Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Atsushi Takahashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Post-Silicon Clock-Timing Tuning Based on Statistical Estimation.

Yuko Hashizume, Yasuhiro Takashima, Yuichi Nakamura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

ILP-based optimization of time-multiplexed I/O assignment for multi-FPGA systems.

Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Atsushi Takahashi

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Fast wire length estimation in obstructive block placement.

Shuting Li, Tan Yan, Yasuhiro Takashima, Hiroshi Murata

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007

A Relocation Method for Circuit Modifications.

Kunihiko Yanagibashi, Yasuhiro Takashima, Yuichi Nakamura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

A Performance-Driven Circuit Bipartitioning Method Considering Time-Multiplexed I/Os.

Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Yoji Kajitani

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

A Theoretical Study on Wire Length Estimation Algorithms for Placement with Opaque Blocks.

Tan Yan, Shuting Li, Yasuhiro Takashima, Hiroshi Murata

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

The Oct-Touched Tile: A New Architecture for Shape-Based Routing.

Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

How does partitioning matter for 3D floorplanning?

Tan Yan, Qing Dong, Yasuhiro Takashima, Yoji Kajitani

Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

A performance-driven circuit bipartitioning algorithm for multi-FPGA implementation with time-multiplexed I/Os.

Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Yoji Kajitani

Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

2004

A fast algorithm for crosspoint assignment under crosstalk constraints with shielding effects.

Keiji Kida, Xiaoke Zhu, Changwen Zhuang, Yasuhiro Takashima, Shigetoshi Nakatake

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A device-level placement with multi-directional convex clustering.

Takashi Nojima, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani

Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Multi-level placement with circuit schema based clustering in analog IC layouts.

Takashi Nojima, Xiaoke Zhu, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Abstraction and optimization of consistent floorplanning with pillar block constraints.

Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2002

Two-dimensional placement method based on divide-and-replacement.

Yasuhiro Takashima, Akira Kaneko, Shinji Sato, Mineo Kaneko

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2000

Self-reforming routing for stochastic search in VLSI interconnection layout.

Yukiko Kubo, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani

Proceedings of ASP-DAC 2000, 2000

1996

Detailed-Routability of FPGAs with Extremal Switch-Block Structures.

Yasuhiro Takashima, Atsushi Takahashi, Yoji Kajitani

Proceedings of the 1996 European Design and Test Conference, 1996