Bo Liu

Affiliations:
  • Beijing Institute of Control Engineering, On-Board Computer and Electronic Technology Laboratory, Beijing, China
  • Chinese Academy of Sciences, Institute of Computing Technology, Beijing, China (PhD 2005)


According to our database1, Bo Liu authored at least 10 papers between 2011 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
Exploring Winograd Convolution for Cost-Effective Neural Network Fault Tolerance.
IEEE Trans. Very Large Scale Integr. Syst., November, 2023

Exploring Winograd Convolution for Cost-effective Neural Network Fault Tolerance.
CoRR, 2023

2018
On Trace Buffer Reuse-Based Trigger Generation in Post-Silicon Debug.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

2017
Flip-flop clustering based trace signal selection for post-silicon debug.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017

2016
Path constraint solving based test generation for observability-enhanced branch coverage.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

An accurate algorithm for computing mutation coverage in model checking.
Proceedings of the 2016 IEEE International Test Conference, 2016

Property Coverage Analysis Based Trustworthiness Verification for Potential Threats from EDA Tools.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

2013
HHC: Hierarchical hardware checkpointing to accelerate fault recovery for SRAM-based FPGAs.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

2012
Off-path leakage power aware routing for SRAM-based FPGAs.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Exploiting Free LUT Entries to Mitigate Soft Errors in SRAM-based FPGAs.
Proceedings of the 20th IEEE Asian Test Symposium, 2011


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