Bo Yi

Orcid: 0000-0002-6596-8480

Affiliations:
  • University of Electronic Science and Technology of China, State Key Laboratory of Electronic Thin Films and Integrated Devices of China, Chengdu, China


According to our database1, Bo Yi authored at least 17 papers between 2019 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2026
A Novel 2.7 kV 3C-SiC/Ga2O3 Hetero-Channel E-mode MISFET With BFOM up to 5.17 GW/cm2.
Microelectron. J., 2026

2025
High-voltage GaN HEMT with self-biased P-GaN VLD layer for improved breakdown voltage and figure of merit.
Microelectron. J., 2025

A new concept high-k GaN FinFET with integrated SBD breaking the unipolar limit of GaN and realizing excellent reverse recovery performance.
Microelectron. J., 2025

2024
Investigations of SiC lateral MOSFET with high-k and equivalent variable lateral doping techniques.
Microelectron. J., 2024

2023
Modeling and simulation of an insulated-gate HEMT using p-SnO<sub>2</sub> gate for high V<sub>TH</sub> design.
Microelectron. J., September, 2023

Comprehensive Comparison of Temperature Performances for SiC Trench MOSFET with Integrated Side-wall Schottky Diode and Heterojunction.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

A Novel 1200-V Class SiC MOSFET With Schottky Barrier Diode for Improved third quadrant performance.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

A Novel SiC Superjunction Trench MOSFET with Integrated Heterojunction Diode for Improved Performance.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

2021
A Vertical Thin Layer pLDMOS with Linear doping realizing ultralow Ron, sp.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

A split-gate SiC trench MOSFET with embedded unipolar diode for improved performances.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

A Novel Trench MOSFET with p-Pillar and RSO Accumulation Layer for Improved Performance.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

A New Ga2O3 Trench Schottky Barrier Diode with Improved Forward Conduction Characteristics.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020
Simulation study of an ultra-low specific on-resistance high-voltage pLDMOS with self-biased accumulation layer.
IEICE Electron. Express, 2020

Lateral Power Fin MOSFET With a High-k Passivation for Ultra-Low On-Resistance.
IEEE Access, 2020

2019
SiC trench MOSFET with integrated side-wall Schottky barrier diode having P<sup>+</sup> electric field shield.
IEICE Electron. Express, 2019

Simulation Study on Novel High Voltage Transient Voltage Suppression Diodes.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

Simulation Study of Trench IGBT with Diode-Clamped P-Well for High dI/dt and dV/dt Controllability.
Proceedings of the 13th IEEE International Conference on ASIC, 2019


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