Junji Cheng

Orcid: 0000-0002-6163-6219

According to our database1, Junji Cheng authored at least 10 papers between 2019 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Modeling and simulation of an insulated-gate HEMT using p-SnO<sub>2</sub> gate for high V<sub>TH</sub> design.
Microelectron. J., September, 2023

Temperature Dependent Optimization for Specific On-Resistance for 900 V Superjunction MOSFETs: Numerical Calculation and Comparison.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

Comprehensive Comparison of Temperature Performances for SiC Trench MOSFET with Integrated Side-wall Schottky Diode and Heterojunction.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

2021
A Vertical Thin Layer pLDMOS with Linear doping realizing ultralow Ron, sp.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

A split-gate SiC trench MOSFET with embedded unipolar diode for improved performances.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020
Simulation study of an ultra-low specific on-resistance high-voltage pLDMOS with self-biased accumulation layer.
IEICE Electron. Express, 2020

Lateral Power Fin MOSFET With a High-k Passivation for Ultra-Low On-Resistance.
IEEE Access, 2020

2019
SiC trench MOSFET with integrated side-wall Schottky barrier diode having P<sup>+</sup> electric field shield.
IEICE Electron. Express, 2019

A novel snapback-free reverse-conducting (RC) SOI-LIGBT with a built-in thyristor.
IEICE Electron. Express, 2019

Analytical Models of Breakdown Voltage and Specific On-Resistance for Vertical GaN Unipolar Devices.
IEEE Access, 2019


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