Bogdan F. Romanescu
According to our database1, Bogdan F. Romanescu authored at least 8 papers between 2007 and 2011.
Legend:Book In proceedings Article PhD thesis Other
Address Translation Aware Memory Consistency.
IEEE Micro, 2011
Cost-effective Designs for Supporting Correct Execution and Scalable Performance in Many-core Processors.
PhD thesis, 2010
UNified Instruction/Translation/Data (UNITD) coherence: One protocol to rule them all.
Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010
Specifying and dynamically verifying address translation-aware memory consistency.
Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, 2010
Reducing the impact of intra-core process variability with criticality-based resource allocation and prefetching.
Proceedings of the 5th Conference on Computing Frontiers, 2008
Core cannibalization architecture: improving lifetime chip performance for multicore processors in the presence of hard faults.
Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, 2008
VariaSim: simulating circuits and systems in the presence of process variability.
SIGARCH Computer Architecture News, 2007
Reducing the Impact of Process Variability with Prefetching and Criticality-Based Resource Allocation.
Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007