Sule Ozev

According to our database1, Sule Ozev authored at least 148 papers between 1999 and 2019.

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Bibliography

2019
Adaptive Test for RF/Analog Circuit Using Higher Order Correlations among Measurements.
ACM Trans. Design Autom. Electr. Syst., 2019

Knowledge- and Simulation-Based Synthesis of Area-Efficient Passive Loop Filter Incremental Zoom-ADC for Built-In Self-Test Applications.
ACM Trans. Design Autom. Electr. Syst., 2019

Contact-Less Near-Field Test of Active Integrated RF Phased Array Antennas.
J. Electronic Testing, 2019

On-Chip RF Phased Array Characterization with DC-Only Measurements for In-Field Calibration.
IEEE Design & Test, 2019

An In-Field Programmable Adaptive CMOS LNA for Intelligent IOT Sensor Node Applications.
CoRR, 2019

Detecting Gas Vapor Leaks Using Uncalibrated Sensors.
IEEE Access, 2019

PCB Hardware Trojans: Attack Modes and Detection Strategies.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Optimized Stress Testing for Flexible Hybrid Electronics Designs.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Detecting Gas Vapor Leaks through Uncalibrated Sensor Based CPS.
Proceedings of the IEEE International Conference on Acoustics, 2019

Digital Built-in Self-Test for Phased Locked Loops to Enable Fault Detection.
Proceedings of the 24th IEEE European Test Symposium, 2019

2018
A Disturbance-Free Built-In Self-Test and Diagnosis Technique for DC-DC Converters.
ACM Trans. Design Autom. Electr. Syst., 2018

Remote Detection of Unauthorized Activity via Spectral Analysis.
ACM Trans. Design Autom. Electr. Syst., 2018

Detection Mechanisms for Unauthorized Wireless Transmissions.
ACM Trans. Design Autom. Electr. Syst., 2018

Online Built-In Self-Test of High Switching Frequency DC-DC Converters Using Model Reference Based System Identification Techniques.
IEEE Trans. on Circuits and Systems, 2018

Special session on BIST/calibration of A/MS devices.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

A built-in self-test technique for transmitter-only systems.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Online information utility assessment for per-device adaptive test flow.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

RF circuit authentication for detection of process Trojans.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Enabling fast process variation and fault simulation through macromodelling of analog components.
Proceedings of the 27th IEEE North Atlantic Test Workshop, 2018

2017
A Comprehensive BIST Solution for Polar Transceivers Using On-Chip Resources.
ACM Trans. Design Autom. Electr. Syst., 2017

Adaptive Reduction of the Frequency Search Space for Multi-Vdd Digital Circuits Using Variation Sensitive Ring Oscillators.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Statistical library characterization using arbitrary polynomial chaos.
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

Built-in self-test for stability measurement of low dropout regulator.
Proceedings of the IEEE International Test Conference, 2017

Evaluation of loop transfer function based dynamic testing of LDOs.
Proceedings of the International Test Conference in Asia, 2017

Receiver echo cancellation with real-time self calibration for passive implanted neuron recorders.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Contact-less near-field measurement of RF phased array antenna mismatches.
Proceedings of the 22nd IEEE European Test Symposium, 2017

Remote detection of unauthorized activity via spectral analysis: work-in-progress.
Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017

2016
A Comparator-Based Rail Clamp.
IEEE Trans. VLSI Syst., 2016

Built-In Self-Test and Digital Calibration of Zero-IF RF Transceivers.
IEEE Trans. VLSI Syst., 2016

Design-Time Reliability Enhancement Using Hotspot Identification for RF Circuits.
IEEE Trans. VLSI Syst., 2016

Process Independent Design Methodology for the Active RC and Single-Inverter-Based Rail Clamp.
ACM Trans. Design Autom. Electr. Syst., 2016

Adapting to Varying Distribution of Unknown Response Bits.
ACM Trans. Design Autom. Electr. Syst., 2016

Rail Clamp with Dynamic Time-Constant Adjustment.
J. Solid-State Circuits, 2016

Process independent gain measurement with low overhead via BIST/DUT co-design.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Making unreliable Chem-FET sensors smart via soft calibration.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Detection of malicious hardware components in mobile platforms.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Post-production adaptation of RF circuits for application-specific performance metrics.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Multi-objective design optimization for flexible hybrid electronics.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

2015
Built-In Self-Test of Transmitter I/Q Mismatch and Nonlinearity Using Self-Mixing Envelope Detector.
IEEE Trans. VLSI Syst., 2015

Adaptive Generation of Unique IDs for Digital Chips through Analog Excitation.
ACM Trans. Design Autom. Electr. Syst., 2015

Adaptive-Learning-Based Importance Sampling for Analog Circuit DPPM Estimation.
IEEE Design & Test, 2015

Panel: Analog/RF BIST: Are we there yet?
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Enabling unauthorized RF transmission below noise floor with no detectable impact on primary communication performance.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Disturbance-free BIST for loop characterization of DC-DC buck converters.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

A self-compensating built-in self-test solution for RF phased array mismatch.
Proceedings of the 2015 IEEE International Test Conference, 2015

Robust amplitude measurement for RF BIST applications.
Proceedings of the 20th IEEE European Test Symposium, 2015

On-chip measurement of bandgap reference voltage using a small form factor VCO based zoom-in ADC.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Built-In EVM Measurement With Negligible Hardware Overhead.
IEEE Design & Test, 2014

Special session 4B: Panel: Testing and calibration for power management circuits.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

A built-in self-test technique for load inductance and lossless current sensing of DC-DC converters.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Development and empirical verification of an accuracy model for the power down leakage tests.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Reliability enhancement using in-field monitoring and recovery for RF circuits.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Built-in self-test and characterization of polar transmitter parameters in the loop-back mode.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Approximating the age of RF/analog circuits through re-characterization and statistical estimation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Per-Device Adaptive Test for Analog/RF Circuits Using Entropy-Based Process Monitoring.
IEEE Trans. VLSI Syst., 2013

Efficient Process Shift Detection and Test Realignment.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Measurement of envelope/phase path delay skew and envelope path bandwidth in polar transmitters.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Zero-overhead self test and calibration of RF transceivers.
Proceedings of the 2013 IEEE International Test Conference, 2013

Adaptive quality binning for analog circuits.
Proceedings of the 18th IEEE European Test Symposium, 2013

Analytical modeling for EVM in OFDM transmitters including the effects of IIP3, I/Q imbalance, noise, AM/AM and AM/PM distortion.
Proceedings of the 18th IEEE European Test Symposium, 2013

Fault analysis and simulation of large scale industrial mixed-signal circuits.
Proceedings of the Design, Automation and Test in Europe, 2013

Adaptive reduction of the frequency search space for multi-vdd digital circuits.
Proceedings of the Design, Automation and Test in Europe, 2013

Electrical calibration of spring-mass MEMS capacitive accelerometers.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Test Application for Analog/RF Circuits With Low Computational Burden.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

Test Signal Development and Analysis for OFDM Systems RF Front-End Parameter Extraction.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

Built-in-Self Test of transmitter I/Q mismatch using self-mixing envelope detector.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Adaptive testing: Conquering process variations.
Proceedings of the 17th IEEE European Test Symposium, 2012

Adaptive multi-site testing for analog/mixed-signal circuits incorporating neighborhood information.
Proceedings of the 17th IEEE European Test Symposium, 2012

Adaptive testing of chips with varying distributions of unknown response bits.
Proceedings of the 17th IEEE European Test Symposium, 2012

An analytical technique for characterization of transceiver IQ imbalances in the loop-back mode.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
A Multi-Site Test Solution for Quadrature Modulation RF Transceivers.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Adaptive Modeling of Analog/RF Circuits for Efficient Fault Response Evaluation.
J. Electronic Testing, 2011

An industrial case study of analog fault modeling.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Adaptive multidimensional outlier analysis for analog and mixed signal circuits.
Proceedings of the 2011 IEEE International Test Conference, 2011

Fast and Accurate DPPM Computation Using Model Based Filtering.
Proceedings of the 16th European Test Symposium, 2011

Analysis and Mitigation of Electromigration in RF Circuits: An LNA Case Study.
Proceedings of the 16th European Test Symposium, 2011

Extraction of EVM from Transmitter System Parameters.
Proceedings of the 16th European Test Symposium, 2011

2010
Detailed Characterization of Transceiver Parameters Through Loop-Back-Based BiST.
IEEE Trans. VLSI Syst., 2010

Low Cost MIMO Testing for RF Integrated Circuits.
IEEE Trans. VLSI Syst., 2010

Adaptive test flow for mixed-signal/RF circuits using learned information from device under test.
Proceedings of the 2011 IEEE International Test Conference, 2010

2009
Wafer-Level Defect Screening for "Big-D/Small-A" Mixed-Signal SoCs.
IEEE Trans. VLSI Syst., 2009

Low-Cost Characterization and Calibration of RF Integrated Circuits through I - Q Data Analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

A Packet Based 2x-Site Test Solution for GSM Transceivers with Limited Tester Resources.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Built-in EVM measurement for OFDM transceivers using all-digital DFT.
Proceedings of the 2009 IEEE International Test Conference, 2009

Defect-based test optimization for analog/RF circuits for near-zero DPPM applications.
Proceedings of the 27th International Conference on Computer Design, 2009

Defect Filter for Alternate RF Test.
Proceedings of the 14th IEEE European Test Symposium, 2009

Adaptive test elimination for analog/RF circuits.
Proceedings of the 46th Design Automation Conference, 2009

2008
Parametric variability analysis for multistage analog circuits using analytical sensitivity modeling.
ACM Trans. Design Autom. Electr. Syst., 2008

Defect-Oriented Testing of RF Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Single-Measurement Diagnostic Test Method for Parametric Faults of I/Q Modulating RF Transceivers.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Optimized EVM Testing for IEEE 802.11a/n RF ICs.
Proceedings of the 2008 IEEE International Test Conference, 2008

Diagnosis of assembly failures for System-in-Package RF tuners.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Dynamic test scheduling for analog circuits for improved test quality.
Proceedings of the 26th International Conference on Computer Design, 2008

Reducing the impact of intra-core process variability with criticality-based resource allocation and prefetching.
Proceedings of the 5th Conference on Computing Frontiers, 2008

2007
Go/No-Go Testing of VCO Modulation RF Transceivers Through the Delayed-RF Setup.
IEEE Trans. VLSI Syst., 2007

Statistical Test Development for Analog Circuits Under High Process Variations.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Online diagnosis of hard faults in microprocessors.
TACO, 2007

VariaSim: simulating circuits and systems in the presence of process variability.
SIGARCH Computer Architecture News, 2007

A Low-Cost RF MIMO Test Method Using a Single Measurement Set-up.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Efficient simulation of parametric faults for multi-stage analog circuits.
Proceedings of the 2007 IEEE International Test Conference, 2007

Test yield estimation for analog/RF circuits over multiple correlated measurements.
Proceedings of the 2007 IEEE International Test Conference, 2007

Low cost characterization of RF transceivers through IQ data analysis.
Proceedings of the 2007 IEEE International Test Conference, 2007

Low-cost run-time diagnosis of hard delay faults in the functional units of a microprocessor.
Proceedings of the 25th International Conference on Computer Design, 2007

Digital calibration of RF transceivers for I-Q imbalances and nonlinearity.
Proceedings of the 25th International Conference on Computer Design, 2007

Lazy Error Detection for Microprocessor Functional Units.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

An ADC-BiST scheme using sequential code analysis.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

AWafer-Level Defect Screening Technique to Reduce Test and Packaging Costs for "Big-D/Small-A" Mixed-Signal SoCs.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Reducing the Impact of Process Variability with Prefetching and Criticality-Based Resource Allocation.
Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007

2006
Test infrastructure design for mixed-signal SOCs with wrapped analog cores.
IEEE Trans. VLSI Syst., 2006

Concurrent testing of digital microfluidics-based biochips.
ACM Trans. Design Autom. Electr. Syst., 2006

Identifying the Source of BW Failures in High-Frequency Linear Analog Circuits Based on S-Parameter Measurements.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Test Planning and Test Resource Optimization for Droplet-Based Microfluidic Systems.
J. Electronic Testing, 2006

Parametric Fault Diagnosis for Analog Circuits Using a Bayesian Framework.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Applying architectural vulnerability Analysis to hard faults in the microprocessor.
Proceedings of the Joint International Conference on Measurement and Modeling of Computer Systems, 2006

Self-Checking and Self-Diagnosing 32-bit Microprocessor Multiplier.
Proceedings of the 2006 IEEE International Test Conference, 2006

A Robust, Self-Tuning CMOS Circuit for Built-in Go/No-Go Testing of Synthesizer Phase Noise.
Proceedings of the 2006 IEEE International Test Conference, 2006

Efficient Testing of RF MIMO Transceivers Used in WLAN Applications.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Enhanced error vector magnitude (EVM) measurements for testing WLAN transceivers.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

2005
Autonomic Microprocessor Execution via Self-Repairing Arrays.
IEEE Trans. Dependable Sec. Comput., 2005

Diagnosis of Failing Component in RF Receivers through Adaptive Full-Path Measurements.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

A Mechanism for Online Diagnosis of Hard Faults in Microprocessors.
Proceedings of the 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-38 2005), 2005

Defect-based RF testing using a new catastrophic fault model.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

A Flexible Design Methodology for Analog Test Wrappers in Mixed-Signal SOCs.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Fast Hierarchical Process Variability Analysis and Parametric Test Development for Analog/RF Circuits.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Parametric test development for RF circuits targeting physical fault locations and using specification-based fault definitions.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores.
Proceedings of the 2005 Design, 2005

Hierarchical Variance Analysis for Analog Circuits Based on Graph Modelling and Correlation Loop Tracing.
Proceedings of the 2005 Design, 2005

Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown.
Proceedings of the 2005 Design, 2005

Hierarchical analysis of process variation for mixed-signal systems.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Design of concurrent test Hardware for Linear analog circuits with constrained hardware overhead.
IEEE Trans. VLSI Syst., 2004

Seamless Test of Digital Components in Mixed-Signal Paths.
IEEE Design & Test of Computers, 2004

Wafer-level RF Test and DfT for VCO Modulating Transceiver Architecures.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Delayed-RF Based Test Development for FM Transceivers Using Signature Analysis.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

End-to-End Testability Analysis and DfT Insertion for Mixed-Signal Paths.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Diagnosis of small-signal parameters for broadband amplifiers through S-parameter measurements and sensitivity-guided evolutionary search.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Tolerating Hard Faults in Microprocessor Array Structures.
Proceedings of the 2004 International Conference on Dependable Systems and Networks (DSN 2004), 28 June, 2004

2003
Statistical Tolerance Analysis for Assured Analog Test Coverage.
J. Electronic Testing, 2003

Testing of Droplet-Based Microelectrofluidic Systems.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

TAM Optimization for Mixed-Signal SOCs using Analog Test Wrappers.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

2002
Multilevel Testability Analysis and Solutions for Integrated Bluetooth Transceivers.
IEEE Design & Test of Computers, 2002

Boosting the Accuracy of Analog Test Coverage Computation through Statistical Tolerance Analysis.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

An Integrated Tool for Analog Test Generation and Fault Simulation.
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

Automated test development and test time reduction for RF subsystems.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Cost-Effective Concurrent Test Hardware Design for Linear Analog Circuits.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

2001
Testability implications in low-cost integrated radio transceivers: a Bluetooth case study.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

2000
Test Selection Based on High Level Fault Simulation for Mixed-Signal Systems.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Test Synthesis for Mixed-Signal SOC Paths.
Proceedings of the 2000 Design, 2000

1999
Low-Cost Test for Large Analog IC's.
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999


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