Bosheng Liu

Orcid: 0000-0001-7123-7425

According to our database1, Bosheng Liu authored at least 19 papers between 2009 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2024
Combining residual structure and edge loss for face image restoration with generative adversarial networks.
Signal Image Video Process., April, 2024

2023
Frequency-Domain Inference Acceleration for Convolutional Neural Networks Using ReRAMs.
IEEE Trans. Parallel Distributed Syst., December, 2023

Two-Level Scheduling Algorithms for Deep Neural Network Inference in Vehicular Networks.
IEEE Trans. Intell. Transp. Syst., September, 2023

Accelerating event-based deep neural networks via flexible data encoding.
IEICE Electron. Express, 2023

Accelerating Convolutional Neural Networks in Frequency Domain via Kernel-Sharing Approach.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022
Search-Free Inference Acceleration for Sparse Convolutional Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2021
Fault Modeling and Efficient Testing of Memristor-Based Memory.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

F3D: Accelerating 3D Convolutional Neural Networks in Frequency Space Using ReRAM.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
Swallow: A Versatile Accelerator for Sparse Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Search-free Accelerator for Sparse Convolutional Neural Networks.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
Accelerating DNN-based 3D point cloud processing for mobile computing.
Sci. China Inf. Sci., 2019

ACG-Engine: An Inference Accelerator for Content Generative Neural Networks.
Proceedings of the International Conference on Computer-Aided Design, 2019

Merging Everything (ME): A Unified FPGA Architecture Based on Logic-in-Memory Techniques.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Addressing the issue of processing element under-utilization in general-purpose systolic deep learning accelerators.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Simulate-the-hardware: training accurate binarized neural networks for low-precision neural accelerators.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2016
C-brain: a deep learning accelerator that tames the diversity of CNNs through adaptive data-level parallelization.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
A signal degradation reduction method for memristor ratioed logic (MRL) gates.
IEICE Electron. Express, 2015

2013
Comparator and half adder design using complementary resistive switches crossbar.
IEICE Electron. Express, 2013

2009
PCE algorithm for PAPR reduction in OFDM-ROF system.
IEEE Trans. Consumer Electron., 2009


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