Zhiqiang You

Orcid: 0000-0001-9924-0685

According to our database1, Zhiqiang You authored at least 36 papers between 2004 and 2023.

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Bibliography

2023
DTTR: Detecting Text with Transformers.
Proceedings of the IEEE International Conference on Acoustics, 2023

2021
Defect Analysis and Parallel Testing for 3D Hybrid CMOS-Memristor Memory.
IEEE Trans. Emerg. Top. Comput., 2021

Integrating Two Logics Into One Crossbar Array for Logic Gate Design.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Fault Modeling and Efficient Testing of Memristor-Based Memory.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

2020
A high-performance CNN method for offline handwritten Chinese character recognition and visualization.
Soft Comput., 2020

2019
Efficient data packet transmission algorithm for IPV6 mobile vehicle network based on fast switching model with time difference.
Future Gener. Comput. Syst., 2019

A Pseudo-Random Transform Decomposition Method for Improving the Coding Compression Ratio of Test Data.
Proceedings of the 21st IEEE International Conference on High Performance Computing and Communications; 17th IEEE International Conference on Smart City; 5th IEEE International Conference on Data Science and Systems, 2019

2018
A novel memristor-based restricted Boltzmann machine for contrastive divergence.
IEICE Electron. Express, 2018

Optimistic value model of multidimensional uncertain optimal control with jump.
Eur. J. Control, 2018

Defect Analysis and Parallel March Test Algorithm for 3D Hybrid CMOS-Memristor Memory.
Proceedings of the 27th IEEE Asian Test Symposium, 2018

2016
A parallel-SSHI rectifier for ultra-low-voltage piezoelectric vibration energy harvesting.
IEICE Electron. Express, 2016

2015
An efficient small-delay faults simulator based on critical path tracing.
Int. J. Circuit Theory Appl., 2015

Logic operation-based DFT method and 1R memristive crossbar March-like test algorithm.
IEICE Electron. Express, 2015

A signal degradation reduction method for memristor ratioed logic (MRL) gates.
IEICE Electron. Express, 2015

Improve the compression ratios for code-based test vector compressions by decomposing.
Proceedings of the 20th IEEE European Test Symposium, 2015

2014
An adaptive neural network A/D converter based on CMOS/memristor hybrid design.
IEICE Electron. Express, 2014

Empirical studies on the network of social groups: the case of Tencent QQ.
CoRR, 2014

2013
A comprehensive metering scheme for intellectual property protection during both after-sale and evaluation periods of IC design.
IEICE Electron. Express, 2013

Comparator and half adder design using complementary resistive switches crossbar.
IEICE Electron. Express, 2013

2012
Achieving low capture and shift power in linear decompressor-based test compression environment.
Microelectron. J., 2012

Virtual scan chains reordering using a RAM-based module for high test compression.
Microelectron. J., 2012

Thermal Simulation of Traction System for High-Speed Train Based on Heat Accumulation.
J. Comput., 2012

A scan disabling-based BAST scheme for test cost and test power reduction.
IEICE Electron. Express, 2012

Switching activity reduction for scan-based BIST using weighted scan input data.
IEICE Electron. Express, 2012

2011
Test data compression using interval broadcast scan for embedded cores.
Microelectron. J., 2011

A scan disabling-based BAST scheme for test cost reduction.
IEICE Electron. Express, 2011

Test Data Compression Using Selective Sparse Storage.
J. Electron. Test., 2011

2010
A GEO-Related IOT Applications Platform Based on Google Map.
Proceedings of the IEEE 7th International Conference on e-Business Engineering, 2010

Test Data Compression Using Four-Coded and Sparse Storage for Testing Embedded Core.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2010

Capture in Turn Scan for Reduction of Test Data Volume, Test Application Time and Test Power.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

2008
Test Response Data Volume and Wire Length Reductions for Extended Compatibilities Scan Tree Construction.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

A Novel BIST Scheme Using Test Vectors Applied by Circuit-under-Test Itself.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

DCScan: A Power-Aware Scan Testing Architecture.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

2006
A Low Power Deterministic Test Using Scan Chain Disable Technique.
IEICE Trans. Inf. Syst., 2006

2005
Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths.
IEICE Trans. Inf. Syst., 2005

2004
Power-Constrained DFT Algorithms for Non-Scan BIST-able RTL Data Paths.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004


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