Krishnendu Chakrabarty

According to our database1, Krishnendu Chakrabarty authored at least 697 papers between 1993 and 2019.

Collaborative distances:

Awards

ACM Fellow

ACM Fellow 2013, "For contributions to optimization methods for system-on-chip test automation, microfluidic biochips, and sensor network infrastructure.".

IEEE Fellow

IEEE Fellow 2008, "For contributions to the testing of core-based system-on-chip integrated circuits".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Homepages:

On csauthors.net:

Bibliography

2019
CAD-Base: An Attack Vector into the Electronics Supply Chain.
ACM Trans. Design Autom. Electr. Syst., 2019

Bio-Protocol Watermarking on Digital Microfluidic Biochips.
IEEE Trans. Information Forensics and Security, 2019

Fault-Tolerant Training Enabled by On-Line Fault Detection for RRAM-Based Neural Computing Systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

Defect Clustering-Aware Spare-TSV Allocation in 3-D ICs for Yield Enhancement.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

Toward Secure and Trustworthy Cyberphysical Microfluidic Biochips.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

Security Assessment of Micro-Electrode-Dot-Array Biochips.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

Optimization of Multi-Target Sample Preparation On-Demand With Digital Microfluidic Biochips.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

A Design-for-Test Solution Based on Dedicated Test Layers and Test Scheduling for Monolithic 3-D Integrated Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

Changepoint-Based Anomaly Detection for Prognostic Diagnosis in a Core Router System.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

Synthesis of a Cyberphysical Hybrid Microfluidic Platform for Single-Cell Analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

Efficient Generation of Dilution Gradients With Digital Microfluidic Biochips.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

Micro-Electrode-Dot-Array Digital Microfluidic Biochips: Technology, Design Automation, and Test Techniques.
IEEE Trans. Biomed. Circuits and Systems, 2019

Randomized Checkpoints: A Practical Defense for Cyber-Physical Microfluidic Systems.
IEEE Design & Test, 2019

Emerging Hardware Techniques and EDA Methodologies for Neuromorphic Computing (Dagstuhl Seminar 19152).
Dagstuhl Reports, 2019

Test-Cost Reduction for 2.5D ICs Using Microspring Technology for Die Attachment and Rework.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Black-Box Test-Coverage Analysis and Test-Cost Reduction Based on a Bayesian Network Model.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Board-Level Functional Fault Identification using Streaming Data.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Reliable Power Delivery and Analysis of Power-Supply Noise During Testing in Monolithic 3D ICs.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Security Assessment of Microfluidic Fully-Programmable-Valve-Array Biochips.
Proceedings of the 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems, 2019

Can Multi-Layer Microfluidic Design Methods Aid Bio-Intellectual Property Protection?
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Test and Design-for-Testability Solutions for Monolithic 3D Integrated Circuits.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Machine Learning-based Prediction of Test Power.
Proceedings of the 24th IEEE European Test Symposium, 2019

Built-in Self-Test for Inter-Layer Vias in Monolithic 3D ICs.
Proceedings of the 24th IEEE European Test Symposium, 2019

Desieve the Attacker: Thwarting IP Theft in Sieve-Valve-based Biochips.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

REGENT: A Heterogeneous ReRAM/GPU-based Architecture Enabled by NoC for Training CNNs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

BioScan: Parameter-Space Exploration of Synthetic Biocircuits Using MEDA Biochips.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Multi-Tenant FPGA-based Reconfigurable Systems: Attacks and Defenses.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

System-level hardware failure prediction using deep learning.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

RTL-to-GDS Tool Flow and Design-for-Test Solutions for Monolithic 3D ICs.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

PREEMPT: PReempting Malware by Examining Embedded Processor Traces.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Security Assessment of Microfluidic Immunoassays.
Proceedings of the International Conference on Omni-Layer Intelligent Systems, 2019

Robust sample preparation on digital microfluidic biochips.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Factorization based dilution of biochemical fluids with micro-electrode-dot-array biochips.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Fault tolerance in neuromorphic computing systems.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Execution of provably secure assays on MEDA biochips to thwart attacks.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Sample preparation for multiple-reactant bioassays on micro-electrode-dot-array biochips.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
Editorial.
IEEE Trans. VLSI Syst., 2018

Fault-Tolerant Unicast-Based Multicast for Reliable Network-on-Chip Testing.
ACM Trans. Design Autom. Electr. Syst., 2018

Multicast Testing of Interposer-Based 2.5D ICs: Test-Architecture Design and Test Scheduling.
ACM Trans. Design Autom. Electr. Syst., 2018

Demand-Driven Single- and Multitarget Mixture Preparation Using Digital Microfluidic Biochips.
ACM Trans. Design Autom. Electr. Syst., 2018

Performance and Thermal Tradeoffs for Energy-Efficient Monolithic 3D Network-on-Chip.
ACM Trans. Design Autom. Electr. Syst., 2018

Adaptive and Roll-Forward Error Recovery in MEDA Biochips Based on Droplet-Aliquot Operations and Predictive Analysis.
IEEE Trans. Multi-Scale Computing Systems, 2018

H2OEIN: A Hierarchical Hybrid Optical/Electrical Interconnection Network for Exascale Computing Systems.
IEEE Trans. Multi-Scale Computing Systems, 2018

Workload-Aware Static Aging Monitoring and Mitigation of Timing-Critical Flip-Flops.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Fine-Grained Aging-Induced Delay Prediction Based on the Monitoring of Run-Time Stress.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Online Soft-Error Vulnerability Estimation for Memory Arrays and Logic Cores.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Leakage Current Analysis for Diagnosis of Bridge Defects in Power-Gating Designs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Secure Randomized Checkpointing for Digital Microfluidic Biochips.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Structural and Functional Test Methods for Micro-Electrode-Dot-Array Digital Microfluidic Biochips.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Efficient and Adaptive Error Recovery in a Micro-Electrode-Dot-Array Digital Microfluidic Biochip.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Toward Predictive Fault Tolerance in a Core-Router System: Anomaly Detection Using Correlation-Based Time-Series Analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Testing 3D-SoCs Using 2-D Time-Division Multiplexing.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Keynote Paper: From EDA to IoT eHealth: Promises, Challenges, and Solutions.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Cyber-Physical Digital-Microfluidic Biochips: Bridging the Gap Between Microfluidics and Microbiology.
Proceedings of the IEEE, 2018

Machine Learning for Hardware Security: Opportunities and Risks.
J. Electronic Testing, 2018

Stuck-at Fault Tolerance in RRAM Computing Systems.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

Broadcast-based minimization of the overall access time for the IEEE 1687 network.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

An inter-layer interconnect BIST solution for monolithic 3D ICs.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Securing IJTAG against data-integrity attacks.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Special session on machine learning for test and diagnosis.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Exact Synthesis of Biomolecular Protocols for Multiple Sample Pathways on Digital Microfluidic Biochips.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

Data-Driven Resiliency Solutions for Boards and Systems.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

Abetting Planned Obsolescence by Aging 3D Networks-on-Chip.
Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018

Access-Time Minimization in the IEEE 1687 Network Using Broadcast and Hardware Parallelism.
Proceedings of the IEEE International Test Conference, 2018

Built-In Self-Diagnosis and Fault-Tolerant Daisy-Chain Design in MEDA Biochips.
Proceedings of the IEEE International Test Conference, 2018

Fault Tolerance for RRAM-Based Matrix Operations.
Proceedings of the IEEE International Test Conference, 2018

Fine-Grained Adaptive Testing Based on Quality Prediction.
Proceedings of the IEEE International Test Conference, 2018

Self-Learning Health-Status Analysis for a Core Router System.
Proceedings of the IEEE International Test Conference, 2018

Analysis of Process Variations, Defects, and Design-Induced Coupling in Memristors.
Proceedings of the IEEE International Test Conference, 2018

Test generation for microfluidic fully programmable valve arrays (FPVAs) with heuristic acceleration.
Proceedings of the 2018 International Conference on IC Design & Technology, 2018

Power-Supply Noise Analysis for Monolithic 3D ICs Using Electrical and Thermal Co-Simulation.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Shadow attacks on MEDA biochips.
Proceedings of the International Conference on Computer-Aided Design, 2018

Failure prediction based on anomaly detection for complex core routers.
Proceedings of the International Conference on Computer-Aided Design, 2018

An efficient fault-tolerant valve-based microfluidic routing fabric for single-cell analysis.
Proceedings of the 23rd IEEE European Test Symposium, 2018

Design of fault-tolerant neuromorphic computing systems.
Proceedings of the 23rd IEEE European Test Symposium, 2018

Locking of biochemical assays for digital microfluidic biochips.
Proceedings of the 23rd IEEE European Test Symposium, 2018

On Designing All-Optical Multipliers Using Mach-Zender Interferometers.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

Fault-tolerant valve-based microfluidic routing fabric for droplet barcoding in single-cell analysis.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Pre-assembly testing of interconnects in embedded multi-die interconnect bridge (EMIB) dies.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Tamper-resistant pin-constrained digital microfluidic biochips.
Proceedings of the 55th Annual Design Automation Conference, 2018

Design-for-testability for continuous-flow microfluidic biochips.
Proceedings of the 55th Annual Design Automation Conference, 2018

Emerging Circuit Technologies: An Overview on the Next Generation of Circuits.
Proceedings of the Advanced Logic Synthesis, 2018

2017
Editorial.
IEEE Trans. VLSI Syst., 2017

Editorial.
IEEE Trans. VLSI Syst., 2017

VFI-Based Power Management to Enhance the Lifetime of High-Performance 3D NoCs.
ACM Trans. Design Autom. Electr. Syst., 2017

Synthesis of Error-Recovery Protocols for Micro-Electrode-Dot-Array Digital Microfluidic Biochips.
ACM Trans. Embedded Comput. Syst., 2017

ExTest Scheduling and Optimization for 2.5-D SoCs With Wrapped Tiles.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Prebond Testing and Test-Path Design for the Silicon Interposer in 2.5-D ICs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

A Branch-&-Bound Test-Access-Mechanism Optimization Method for Multi-Vdd SoCs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Synthesis of Cyberphysical Digital-Microfluidic Biochips for Real-Time Quantitative Analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Control-Layer Routing and Control-Pin Minimization for Flow-Based Microfluidic Biochips.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Design-Space Exploration and Optimization of an Energy-Efficient and Reliable 3-D Small-World Network-on-Chip.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Adaptation of Biochemical Protocols to Handle Technology-Change for Digital Microfluidics.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Droplet Size-Aware High-Level Synthesis for Micro-Electrode-Dot-Array Digital Microfluidic Biochips.
IEEE Trans. Biomed. Circuits and Systems, 2017

Droplet Size-Aware and Error-Correcting Sample Preparation Using Micro-Electrode-Dot-Array Digital Microfluidic Biochips.
IEEE Trans. Biomed. Circuits and Systems, 2017

Microfluidic Biochips: Bridging Biochemistry with Computer Science and Engineering (NII Shonan Meeting 2017-1).
NII Shonan Meet. Rep., 2017

Impact of Electrostatic Coupling and Wafer-Bonding Defects on Delay Testing of Monolithic 3D Integrated Circuits.
JETC, 2017

Offline Error Detection in MEDA-Based Digital Microfluidic Biochips Using Oscillation-Based Testing Methodology.
J. Electronic Testing, 2017

Tackling Test Challenges for Interposer-Based 2.5-D Integrated Circuits.
IEEE Design & Test, 2017

Quo Vadis Test? The Past, the Present, and the Future: No Longer a Necessary Evil.
IEEE Design & Test, 2017

Testing Microfluidic Fully Programmable Valve Arrays (FPVAs).
CoRR, 2017

Test-cost optimization in a scan-compression architecture using support-vector regression.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017

Software-based online self-testing of network-on-chip using bounded model checking.
Proceedings of the IEEE International Test Conference, 2017

Symbol-based health-status analysis in a core router system.
Proceedings of the IEEE International Test Conference, 2017

Changepoint-based anomaly detection in a core router system.
Proceedings of the IEEE International Test Conference, 2017

Run-time hardware trojan detection using performance counters.
Proceedings of the IEEE International Test Conference, 2017

Sample Preparation on Micro-Electrode-Dot-Array Digital Microfluidic Biochips.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Security Trade-Offs in Microfluidic Routing Fabrics.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

A Design-for-Test Solution for Monolithic 3D Integrated Circuits.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Monolithic 3D-Enabled High Performance and Energy Efficient Network-on-Chip.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Adaptive error recovery in MEDA biochips based on droplet-aliquot operations and predictive analysis.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Sortex: Efficient timing-driven synthesis of reconfigurable flow-based biochips for scalable single-cell screening.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Design automation and testing of monolithic 3D ICs: Opportunities, challenges, and solutions: (Invited paper).
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Testing microfluidic Fully Programmable Valve Arrays (FPVAs).
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

CoSyn: Efficient single-cell analysis using a hybrid microfluidic platform.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Digital-microfluidic biochips for quantitative analysis: Bridging the Gap between microfluidics and microbiology.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Optimization of retargeting for IEEE 1149.1 TAP controllers with embedded compression.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Robust TSV-based 3D NoC design to counteract electromigration and crosstalk noise.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Fault-Tolerant Training with On-Line Fault Detection for RRAM-Based Neural Computing Systems.
Proceedings of the 54th Annual Design Automation Conference, 2017

Data analytics enables energy-efficiency and robustness: from mobile to manycores, datacenters, and networks (special session paper).
Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017

Security Implications of Cyberphysical Flow-Based Microfluidic Biochips.
Proceedings of the 26th IEEE Asian Test Symposium, 2017

Workload-aware static aging monitoring of timing-critical flip-flops.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Exact routing for micro-electrode-dot-array digital microfluidic biochips.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Computation-oriented fault-tolerance schemes for RRAM computing systems.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Editorial First TVLSI Best AE and Reviewer Awards.
IEEE Trans. VLSI Syst., 2016

Error-Correcting Sample Preparation with Cyberphysical Digital Microfluidic Lab-on-Chip.
ACM Trans. Design Autom. Electr. Syst., 2016

Optimization of 3D Digital Microfluidic Biochips for the Multiplexed Polymerase Chain Reaction.
ACM Trans. Design Autom. Electr. Syst., 2016

Security Assessment of Cyberphysical Digital Microfluidic Biochips.
IEEE/ACM Trans. Comput. Biology Bioinform., 2016

Adaptive Board-Level Functional Fault Diagnosis Using Incremental Decision Trees.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

On-Chip Droop-Induced Circuit Delay Prediction Based on Support-Vector Machines.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

A Novel Test Method for Metallic CNTs in CNFET-Based SRAMs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Efficient Board-Level Functional Fault Diagnosis With Missing Syndromes.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Wash Optimization and Analysis for Cross-Contamination Removal Under Physical Constraints in Flow-Based Microfluidic Biochips.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Fault Diagnosis for Leakage and Blockage Defects in Flow-Based Microfluidic Biochips.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

A Distributed, Reconfigurable, and Reusable BIST Infrastructure for Test and Diagnosis of 3-D-Stacked ICs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Multicast-Based Testing and Thermal-Aware Test Scheduling for 3D ICs with a Stacked Network-on-Chip.
IEEE Trans. Computers, 2016

Design-Space Exploration and Optimization of an Energy-Efficient and Reliable 3D Small-world Network-on-Chip.
CoRR, 2016

Digital-Microfluidic Biochips.
IEEE Computer, 2016

Supply-Chain Security of Digital Microfluidic Biochips.
IEEE Computer, 2016

A programmable method for low-power scan shift in SoC integrated circuits.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Online soft-error vulnerability estimation for memory arrays.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Optimization of the IEEE 1687 access network for hybrid access schedules.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Foreword.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

The hype, myths, and realities of testing 2.5D/3D integrated circuits.
Proceedings of the 17th Latin-American Test Symposium, 2016

A unified test and fault-tolerant multicast solution for network-on-chip designs.
Proceedings of the 2016 IEEE International Test Conference, 2016

Testing of interposer-based 2.5D integrated circuits.
Proceedings of the 2016 IEEE International Test Conference, 2016

Securing digital microfluidic biochips by randomizing checkpoints.
Proceedings of the 2016 IEEE International Test Conference, 2016

Built-in self-test for micro-electrode-dot-array digital microfluidic biochips.
Proceedings of the 2016 IEEE International Test Conference, 2016

Defect tolerance for CNFET-based SRAMs.
Proceedings of the 2016 IEEE International Test Conference, 2016

Supply-voltage optimization to account for process variations in high-volume manufacturing testing.
Proceedings of the 2016 IEEE International Test Conference, 2016

Accurate anomaly detection using correlation-based time-series analysis in a core router system.
Proceedings of the 2016 IEEE International Test Conference, 2016

The hype, myths, and realities of testing 3D integrated circuits.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Error recovery in a micro-electrode-dot-array digital microfluidic biochip?
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Energy-efficient and reliable 3D network-on-chip (NoC): architectures and optimization algorithms.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

A design-for-test solution for monolithic 3D integrated circuits.
Proceedings of the 21th IEEE European Test Symposium, 2016

Analysis of electrostatic coupling in monolithic 3D integrated circuits and its impact on delay testing.
Proceedings of the 21th IEEE European Test Symposium, 2016

Two-dimensional time-division multiplexing for 3D-SoCs.
Proceedings of the 21th IEEE European Test Symposium, 2016

Thermal-aware TSV repair for electromigration in 3D ICs.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Pre-bond testing of the silicon interposer in 2.5D ICs.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Integrated and real-time quantitative analysis using cyberphysical digital-microfluidic biochips.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Reliability and performance trade-offs for 3D NoC-enabled multicore chips.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

High-level synthesis for micro-electrode-dot-array digital microfluidic biochips.
Proceedings of the 53rd Annual Design Automation Conference, 2016

A real-time digital-microfluidic platform for epigenetics.
Proceedings of the 2016 International Conference on Compilers, 2016

Cyberphysical adaptation in digital-microfluidic biochips.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016

Microfluidic encryption of on-chip biochemical assays.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016

Multicast Test Architecture and Test Scheduling for Interposer-Based 2.5D ICs.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

Testing of Interposer-Based 2.5D Integrated Circuits: Challenges and Solutions.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

Test and Reliability Issues in 2.5D and 3D Integration.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015
Scan Test of Die Logic in 3-D ICs Using TSV Probing.
IEEE Trans. VLSI Syst., 2015

Built-In Self-Test and Test Scheduling for Interposer-Based 2.5D IC.
ACM Trans. Design Autom. Electr. Syst., 2015

Offline Washing Schemes for Residue Removal in Digital Microfluidic Biochips.
ACM Trans. Design Autom. Electr. Syst., 2015

Aging- and Variation-Aware Delay Monitoring Using Representative Critical Path Selection.
ACM Trans. Design Autom. Electr. Syst., 2015

Data-Driven Optimization of Order Admission Policies in a Digital Print Factory.
ACM Trans. Design Autom. Electr. Syst., 2015

Accurate Analysis and Prediction of Enterprise Service-Level Performance.
ACM Trans. Design Autom. Electr. Syst., 2015

Layout-Aware Mixture Preparation of Biochemical Fluids on Application-Specific Digital Microfluidic Biochips.
ACM Trans. Design Autom. Electr. Syst., 2015

Efficient Error Recovery in Cyberphysical Digital-Microfluidic Biochips.
IEEE Trans. Multi-Scale Computing Systems, 2015

Information-Theoretic Syndrome Evaluation, Statistical Root-Cause Analysis, and Correlation-Based Feature Selection for Guiding Board-Level Fault Diagnosis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Interconnect Testing and Test-Path Scheduling for Interposer-Based 2.5-D ICs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Time-Division Multiplexing for Testing DVFS-Based SoCs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Design and Optimization of a Cyberphysical Digital-Microfluidic Biochip for the Polymerase Chain Reaction.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Accurate Predictions of Process-Execution Time and Process Status Based on Support-Vector Regression for Enterprise Information Systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Robust Optimization of Test-Access Architectures Under Realistic Scenarios.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Reuse-Based Optimization for Prebond and Post-Bond Testing of 3-D-Stacked ICs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Test-Cost Modeling and Optimal Test-Flow Selection of 3-D-Stacked ICs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Real-Time Production Scheduler for Digital-Print-Service Providers Based on a Dynamic Incremental Evolutionary Algorithm.
IEEE Trans. Automation Science and Engineering, 2015

Waste-aware single-target dilution of a biochemical fluid using digital microfluidic biochips.
Integration, 2015

Continuous-Flow Biochips: Technology, Physical-Design Methods, and Testing.
IEEE Design & Test, 2015

Design of Microfluidic Biochips (Dagstuhl Seminar 15352).
Dagstuhl Reports, 2015

ExTest scheduling for 2.5D system-on-chip integrated circuits.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Fault diagnosis for flow-based microfluidic biochips.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Advances in Design Automation Techniques for Digital-Microfluidic Biochips.
Proceedings of the Formal Modeling and Verification of Cyber-Physical Systems, 2015

Test-access-mechanism optimization for multi-Vdd SoCs.
Proceedings of the 2015 IEEE International Test Conference, 2015

Efficient observation-point insertion for diagnosability enhancement in digital circuits.
Proceedings of the 2015 IEEE International Test Conference, 2015

A general testing method for digital microfluidic biochips under physical constraints.
Proceedings of the 2015 IEEE International Test Conference, 2015

Test and debug solutions for 3D-stacked integrated circuits.
Proceedings of the 2015 IEEE International Test Conference, 2015

Contactless pre-bond TSV fault diagnosis using duty-cycle detectors and ring oscillators.
Proceedings of the 2015 IEEE International Test Conference, 2015

Self-awareness and self-learning for resiliency in real-time systems.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

Cyber-physical integration in programmable microfluidic biochips.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Security implications of cyberphysical digital microfluidic biochips.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Defect Clustering-Aware Spare-TSV Allocation for 3D ICs.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Fine-Grained Aging Prediction Based on the Monitoring of Run-Time Stress Using DfT Infrastructure.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

A General and Exact Routing Methodology for Digital Microfluidic Biochips.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Optimizing 3D NoC Design for Energy Efficiency: A Machine Learning Approach.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Digital Microfluidic Biochips: Towards Functional Diversity, More than Moore, and Cyberphysical Integration.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

A branch-&-bound algorithm for TAM optimization in multi-Vdd SoCs.
Proceedings of the 20th IEEE European Test Symposium, 2015

Re-using BIST for circuit aging monitoring.
Proceedings of the 20th IEEE European Test Symposium, 2015

Testing of digital microfluidic biochips with arbitrary layouts.
Proceedings of the 20th IEEE European Test Symposium, 2015

Microfluidic very large-scale integration for biochips: Technology, testing and fault-tolerant design.
Proceedings of the 20th IEEE European Test Symposium, 2015

An online thermal-constrained task scheduler for 3D multi-core processors.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Error recovery in digital microfluidics for personalized medicine.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Jump test for metallic CNTs in CNFET-based SRAM.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Experimental demonstration of error recovery in an integrated cyberphysical digital-microfluidic platform.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015

Self-learning and adaptive board-level functional fault diagnosis.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Design and optimization of 3D digital microfluidic biochips for the polymerase chain reaction.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Software-based test and diagnosis of SoCs using embedded and wide-I/O DRAM.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Hardware/Software Co-Design and Optimization for Cyberphysical Integration in Digital Microfluidic Biochips.
Springer, ISBN: 978-3-319-09005-4, 2015

Data-Driven Optimization and Knowledge Discovery for an Enterprise Information System.
Springer, ISBN: 978-3-319-18737-2, 2015

2014
Static Power Reduction Using Variation-Tolerant and Reconfigurable Multi-Mode Power Switches.
IEEE Trans. VLSI Syst., 2014

Testing of TSV-Induced Small Delay Faults for 3-D Integrated Circuits.
IEEE Trans. VLSI Syst., 2014

Delay Test for Diagnosis of Power Switches.
IEEE Trans. VLSI Syst., 2014

Board-Level Functional Fault Diagnosis Using Multikernel Support Vector Machines and Incremental Learning.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Built-In Self-Test, Diagnosis, and Repair of MultiMode Power Switches.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Scan-Based Testing of Post-Bond Silicon Interposer Interconnects in 2.5-D ICs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Retiming for Delay Recovery After DfT Insertion on Interdie Paths in 3-D ICs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

On-Chip Sample Preparation for Multiple Targets Using Digital Microfluidics.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Biochemistry Synthesis on a Cyberphysical Digital Microfluidics Platform Under Completion-Time Uncertainties in Fluidic Operations.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Testing of Flow-Based Microfluidic Biochips: Fault Modeling, Test Generation, and Experimental Demonstration.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Biochip Synthesis and Dynamic Error Recovery for Sample Preparation Using Digital Microfluidics.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Contactless Pre-Bond TSV Test and Diagnosis Using Ring Oscillators and Multiple Voltage Levels.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Test-Delivery Optimization in Manycore SOCs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Optimization of Test Pin-Count, Test Scheduling, and Test Access for NoC-Based Multicore SoCs.
IEEE Trans. Computers, 2014

An Optimal Two-Mixer Dilution Engine with Digital Microfluidics for Low-Power Applications.
J. Low Power Electronics, 2014

Theory and analysis of generalized mixing and dilution of biochemical fluids using digital microfluidic biochips.
JETC, 2014

Test and Design-for-Testability Solutions for 3D Integrated Circuits.
IPSJ Trans. System LSI Design Methodology, 2014

High-throughput dilution engine for sample preparation on digital microfluidic biochips.
IET Computers & Digital Techniques, 2014

Efficient LFSR Reseeding Based on Internal-Response Feedback.
J. Electronic Testing, 2014

Information-Theoretic Framework for Evaluating and Guiding Board-Level Functional-Fault Diagnosis.
IEEE Design & Test, 2014

On-chip voltage-droop prediction using support-vector machines.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

At-speed interconnect testing and test-path optimization for 2.5D ICs.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Test generation and design-for-testability for flow-based mVLSI microfluidic biochips.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Test-time optimization in NOC-based manycore SOCs using multicast routing.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Tutorial T5: Microfluidic Biochips: Connecting VLSI and Embedded Systems to the Life Sciences.
Proceedings of the 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014

Correctness Checking of Bio-chemical Protocol Realizations on a Digital Microfluidic Biochip.
Proceedings of the 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014

Output selection for test response compaction based on multiple counters.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

Knowledge discovery and knowledge transfer in board-level functional fault diagnosis.
Proceedings of the 2014 International Test Conference, 2014

Massive signal tracing using on-chip DRAM for in-system silicon debug.
Proceedings of the 2014 International Test Conference, 2014

A distributed, reconfigurable, and reusable bist infrastructure for 3D-stacked ICs.
Proceedings of the 2014 International Test Conference, 2014

Chip Health Monitoring Using Machine Learning.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Built-in self-test for interposer-based 2.5D ICs.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Design automation for biochemistry synthesis on a digital microfluidic lab-on-a-chip.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Output-bit selection with X-avoidance using multiple counters for test-response compaction.
Proceedings of the 19th IEEE European Test Symposium, 2014

Recent advances in single- and multi-site test optimization for DVS-based SoCs.
Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

Multi-site test optimization for multi-Vdd SoCs using space- and time- division multiplexing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Demand-Driven Mixture Preparation and Droplet Streaming using Digital Microfluidic Biochips.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Control-layer optimization for flow-based mVLSI microfluidic biochips.
Proceedings of the 2014 International Conference on Compilers, 2014

Reliability-Driven Pipelined Scan-Like Testing of Digital Microfluidic Biochips.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

Adaptive Mitigation of Parameter Variations.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

Wash optimization for cross-contamination removal in flow-based microfluidic biochips.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs.
Springer, ISBN: 978-3-319-02377-9, 2014

2013
Crosstalk- and Process Variations-Aware High-Quality Tests for Small-Delay Defects.
IEEE Trans. VLSI Syst., 2013

Test compaction for small-delay defects using an effective path selection scheme.
ACM Trans. Design Autom. Electr. Syst., 2013

Board-Level Functional Fault Diagnosis Using Artificial Neural Networks, Support-Vector Machines, and Weighted-Majority Voting.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Pre-Bond Probing of Through-Silicon Vias in 3-D Stacked ICs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Real-Time Error Recovery in Cyberphysical Digital-Microfluidic Biochips Using a Compact Dictionary.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Error Recovery in Cyberphysical Digital Microfluidic Biochips.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Design of Pin-Constrained General-Purpose Digital Microfluidic Biochips.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Counter-Based Output Selection for Test Response Compaction.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Detection, Diagnosis, and Recovery From Clock-Domain Crossing Failures in Multiclock SoCs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Generation of Effective 1-Detect TDF Patterns for Detecting Small-Delay Defects.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Control of Chaos in Current Controlled DC Drives.
Journal of Circuits, Systems, and Computers, 2013

Efficient Pattern Generation for Small-Delay Defects Using Selection of Critical Faults.
J. Electronic Testing, 2013

Algorithms for Producing Linear Dilution Gradient with Digital Microfluidics.
CoRR, 2013

Post-DfT-insertion retiming for delay recovery on inter-die paths in 3D ICs.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Testing of flow-based microfluidic biochips.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Test-cost optimization and test-flow selection for 3D-stacked ICs.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Thermal-aware test scheduling for NOC-based 3D integrated circuits.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

On-Chip Dilution from Multiple Concentrations of a Sample Fluid Using Digital Microfluidics.
Proceedings of the VLSI Design and Test, 17th International Symposium, 2013

Representative critical-path selection for aging-induced delay monitoring.
Proceedings of the 2013 IEEE International Test Conference, 2013

Uncertainty-aware robust optimization of test-access architectures for 3D stacked ICs.
Proceedings of the 2013 IEEE International Test Conference, 2013

A graph-theoretic approach for minimizing the number of wrapper cells for pre-bond testing of 3D-stacked ICs.
Proceedings of the 2013 IEEE International Test Conference, 2013

Routing-aware resource allocation for mixture preparation in digital microfluidic biochips.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

On Producing Linear Dilution Gradient of a Sample with a Digital Microfluidic Biochip.
Proceedings of the 2013 International Symposium on Electronic System Design, 2013

Optimal Two-Mixer Scheduling in Dilution Engine on a Digital Microfluidic Biochip.
Proceedings of the 2013 International Symposium on Electronic System Design, 2013

Optimization of polymerase chain reaction on a cyberphysical digital microfluidic biochip.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Information-theoretic syndrome and root-cause analysis for guiding board-level fault diagnosis.
Proceedings of the 18th IEEE European Test Symposium, 2013

Robust optimization of test-architecture designs for core-based SoCs.
Proceedings of the 18th IEEE European Test Symposium, 2013

Efficient mixture preparation on digital microfluidic biochips.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

Testing for SoCs with advanced static and dynamic power-management capabilities.
Proceedings of the Design, Automation and Test in Europe, 2013

Fault detection, real-time error recovery, and experimental demonstration for digital microfluidic biochips.
Proceedings of the Design, Automation and Test in Europe, 2013

Non-invasive pre-bond TSV test using ring oscillators and multiple voltage levels.
Proceedings of the Design, Automation and Test in Europe, 2013

Design of cyberphysical digital microfluidic biochips under completion-time uncertainties in fluidic operations.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

On effective and efficient in-field TSV repair for stacked 3D ICs.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Handling Missing Syndromes in Board-Level Functional-Fault Diagnosis.
Proceedings of the 22nd Asian Test Symposium, 2013

Post-bond Testing of the Silicon Interposer and Micro-bumps in 2.5D ICs.
Proceedings of the 22nd Asian Test Symposium, 2013

Test Generation of Path Delay Faults Induced by Defects in Power TSV.
Proceedings of the 22nd Asian Test Symposium, 2013

A New LFSR Reseeding Scheme via Internal Response Feedback.
Proceedings of the 22nd Asian Test Symposium, 2013

Face-to-face bus design with built-in self-test in 3D ICs.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012
Optimization Techniques for the Synchronization of Concurrent Fluidic Operations in Pin-Constrained Digital Microfluidic Biochips.
IEEE Trans. VLSI Syst., 2012

Physical-Defect Modeling and Optimization for Fault-Insertion Test.
IEEE Trans. VLSI Syst., 2012

Integrated Test-Architecture Optimization and Thermal-Aware Test Scheduling for 3-D SoCs Under Pre-Bond Test-Pin-Count Constraint.
IEEE Trans. VLSI Syst., 2012

Functional Test-Sequence Grading at Register-Transfer Level.
IEEE Trans. VLSI Syst., 2012

Cross-Contamination Avoidance for Droplet Routing in Digital Microfluidic Biochips.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

Simultaneous Optimization of Droplet Routing and Control-Pin Mapping to Electrodes in Digital Microfluidic Biochips.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

Test Schedule Optimization for Multicore SoCs: Handling Dynamic Voltage Scaling and Multiple Voltage Islands.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

A Reagent-Saving Mixing Algorithm for Preparing Multiple-Target Biochemical Samples Using Digital Microfluidics.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

Diagnosis of Board-Level Functional Failures Under Uncertainty Using Dempster-Shafer Theory.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

Reproduction and Detection of Board-Level Functional Failure.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

Congestion-aware layout design for high-throughput digital microfluidic biochips.
JETC, 2012

Testing of Low-cost Digital Microfluidic Biochips with Non-Regular Array Layouts.
J. Electronic Testing, 2012

Optimization Methods for Post-Bond Testing of 3D Stacked ICs.
J. Electronic Testing, 2012

Towards more digital content in wireless systems [From the EiC].
IEEE Design & Test of Computers, 2012

Electronic Design Methods and Technologies for Green Buildings.
IEEE Design & Test of Computers, 2012

Looking ahead at the role of electronic design automation in synthetic biology [From the EIC].
IEEE Design & Test of Computers, 2012

Standards, Interoperability, and Innovation in a Disaggregated IC Industry.
IEEE Design & Test of Computers, 2012

The Quest for High-Yield IC Manufacturing.
IEEE Design & Test of Computers, 2012

Ping-pong test: Compact test vector generation for reversible circuits.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

3D IC test scheduling using simulated annealing.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

Scan test of die logic in 3D ICs using TSV probing.
Proceedings of the 2012 IEEE International Test Conference, 2012

A dynamic programming solution for optimizing test delivery in multicore SOCs.
Proceedings of the 2012 IEEE International Test Conference, 2012

On-Chip Sample Preparation with Multiple Dilutions Using Digital Microfluidics.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Low-Cost Dilution Engine for Sample Preparation in Digital Microfluidic Biochips.
Proceedings of the International Symposium on Electronic System Design, 2012

Accumulator-based output selection for test response compaction.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Design methodology for sample preparation on digital microfluidic biochips.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Dictionary-based error recovery in cyberphysical digital-microfluidic biochips.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Diagnostic system based on support-vector machines for board-level functional diagnosis.
Proceedings of the 17th IEEE European Test Symposium, 2012

Time-division multiplexing for testing SoCs with DVS and multiple voltage islands.
Proceedings of the 17th IEEE European Test Symposium, 2012

Re-using chip level DFT at board level.
Proceedings of the 17th IEEE European Test Symposium, 2012

Test pin count reduction for NoC-based Test delivery in multicore SOCs.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

A cyberphysical synthesis approach for error recovery in digital microfluidic biochips.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Test generation for clock-domain crossing faults in integrated circuits.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

TSV open defects in 3D integrated circuits: characterization, test, and optimal spare allocation.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Design of pin-constrained general-purpose digital microfluidic biochips.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Automated path planning for washing in digital microfluidic biochips.
Proceedings of the 2012 IEEE International Conference on Automation Science and Engineering, 2012

Board-Level Functional Fault Diagnosis Using Learning Based on Incremental Support-Vector Machines.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

Adaptive Board-Level Functional Fault Diagnosis Using Decision Trees.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

On-Line Error Detection in Digital Microfluidic Biochips.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

Reduced-Complexity Transition-Fault Test Generation for Non-scan Circuits through High-Level Mutant Injection.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

Robust Timing-Aware Test Generation Using Pseudo-Boolean Optimization.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

TSV Stress-Aware ATPG for 3D Stacked ICs.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

Design and Testing of Digital Microfluidic Biochips.
Springer, ISBN: 978-1-4614-0369-2, 2012

2011
Defect-Oriented LFSR Reseeding to Target Unmodeled Defects Using Stuck-at Test Sets.
IEEE Trans. VLSI Syst., 2011

Broadcast Electrode-Addressing and Scheduling Methods for Pin-Constrained Digital Microfluidic Biochips.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D Stacked ICs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Generation of Compact Stuck-At Test Sets Targeting Unmodeled Defects.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

MVP: Minimum-Violations Partitioning for Reducing Capture Power in At-Speed Delay-Fault Testing.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

P2DAP - Sybil Attacks Detection in Vehicular Ad Hoc Networks.
IEEE Journal on Selected Areas in Communications, 2011

Test-wrapper optimisation for embedded cores in through-silicon via-based three-dimensional system on chips.
IET Computers & Digital Techniques, 2011

Fault Diagnosis in Lab-on-Chip Using Digital Microfluidic Logic Gates.
J. Electronic Testing, 2011

Guest Editorial.
J. Electronic Testing, 2011

Test Planning in Digital Microfluidic Biochips Using Efficient Eulerization Techniques.
J. Electronic Testing, 2011

A Metric to Target Small-Delay Defects in Industrial Circuits.
IEEE Design & Test of Computers, 2011

A Robust and Reconfigurable Multi-mode Power Gating Architecture.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

Layout-Aware Solution Preparation for Biochemical Analysis on a Digital Microfluidic Biochip.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

Design and optimization methods for digital microfluidic biochips: A vision for functional diversity and more than moore.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

Smart diagnosis: Efficient board-level diagnosis and repair using artificial neural networks.
Proceedings of the 2011 IEEE International Test Conference, 2011

Pre-bond probing of TSVs in 3D stacked ICs.
Proceedings of the 2011 IEEE International Test Conference, 2011

Co-optimization of droplet routing and pin assignment in disposable digital microfluidic biochips.
Proceedings of the 2011 International Symposium on Physical Design, 2011

A BIST scheme for testing and repair of multi-mode power switches.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Reliability-oriented broadcast electrode-addressing for pin-constrained digital microfluidic biochips.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

The role of EDA in digital print automation and infrastructure optimization.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

On residue removal in digital microfluidic biochips.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Signature Analysis for Testing, Diagnosis, and Repair of Multi-mode Power Switches.
Proceedings of the 16th European Test Symposium, 2011

Ranking of Suspect Faulty Blocks Using Dataflow Analysis and Dempster-Shafer Theory for the Diagnosis of Board-Level Functional Failures.
Proceedings of the 16th European Test Symposium, 2011

Critical Fault-Based Pattern Generation for Screening SDDs.
Proceedings of the 16th European Test Symposium, 2011

Testing and design-for-testability solutions for 3D integrated circuits.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Waste-aware dilution and mixing of biochemical samples with digital microfluidic biochips.
Proceedings of the Design, Automation and Test in Europe, 2011

Digital microfluidic biochips: recent research and emerging challenges.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

Digital microfluidic biochips: functional diversity, more than moore, and cyberphysical systems.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

Analysis of Resistive Bridge Defect Delay Behavior in the Presence of Process Variation.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

Testing and Design-for-Testability Techniques for 3D Integrated Circuits.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

Identification of Defective TSVs in Pre-Bond Testing of 3D ICs.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

Test Scheduling for Multicore SoCs with Dynamic Voltage Scaling and Multiple Voltage Islands.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

Testing of Clock-Domain Crossing Faults in Multi-core System-on-Chip.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

On Generation of 1-Detect TDF Pattern Set with Significantly Increased SDD Coverage.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

Deterministic test for the reproduction and detection of board-level functional failures.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

3D-Scalable Adaptive Scan (3D-SAS).
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

Pre-bond testing of die logic and TSVs in high performance 3D-SICs.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

Test Infrastructure Design - for Digital, Mixed-Signal and Hierarchical SOCs.
LAP Lambert Academic Publishing, ISBN: 978-3-8433-7359-3, 2011

Test and Diagnosis for Small-Delay Defects.
Springer, ISBN: 978-1-4419-8296-4, 2011

2010
Design Automation and Test Solutions for Digital Microfluidic Biochips.
IEEE Trans. on Circuits and Systems, 2010

Test-Pattern Selection for Screening Small-Delay Defects in Very-Deep Submicrometer Integrated Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

Defect-Tolerant Design and Optimization of a Digital Microfluidic Biochip for Protein Crystallization.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

Optimization of Dilution and Mixing of Biochemical Samples Using Digital Microfluidic Biochips.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

Gate-Sizing-Based Single Vdd Test for Bridge Defects in Multivoltage Designs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

Design Tools for Digital Microfluidic Biochips: Toward Functional Diversification and More Than Moore.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

Digital Microfluidic Logic Gates and Their Application to Built-in Self-Test of Lab-on-Chip.
IEEE Trans. Biomed. Circuits and Systems, 2010

Test-access mechanism optimization for core-based three-dimensional SOCs.
Microelectronics Journal, 2010

Integrated control-path design and error recovery in the synthesis of digital microfluidic lab-on-chip.
JETC, 2010

Editorial.
JETC, 2010

Datacollection in Event-Driven Wireless Sensor Networks with Mobile Sinks.
IJDSN, 2010

An Energy-Efficient Data Delivery Scheme for Delay-Sensitive Traffic in Wireless Sensor Networks.
IJDSN, 2010

RTL DFT Techniques to Enhance Defect Coverage for Functional Test Sequences.
J. Electronic Testing, 2010

Pin-count-aware online testing of digital microfluidic biochips.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Board-level fault diagnosis using Bayesian inference.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

A novel hybrid method for SDD pattern grading and selection.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Synchronization of Concurrently-Implemented Fluidic Operations in Pin-Constrained Digital Microfluidic Biochips.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

Digital Microfluidic Biochips: A Vision for Functional Diversity and More than Moore.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

Board-level fault diagnosis using an error-flow dictionary.
Proceedings of the 2011 IEEE International Test Conference, 2010

RT-level design-for-testability and expansion of functional test sequences for enhanced defect coverage.
Proceedings of the 2011 IEEE International Test Conference, 2010

Optimization methods for post-bond die-internal/external testing in 3D stacked ICs.
Proceedings of the 2011 IEEE International Test Conference, 2010

Digital Microfluidic Biochips: A Vision for Functional Diversity and More than Moore.
Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010

Digital microfluidic biochips: A vision for functional diversity and more than moore.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

MVP: Capture-power reduction with minimum-violations partitioning for delay testing.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Test-architecture optimization for TSV-based 3D stacked ICs.
Proceedings of the 15th European Test Symposium, 2010

Soft error-aware design optimization of low power and time-constrained embedded systems.
Proceedings of the Design, Automation and Test in Europe, 2010

High-quality pattern selection for screening small-delay defects considering process variations and crosstalk.
Proceedings of the Design, Automation and Test in Europe, 2010

Defect aware X-filling for low-power scan testing.
Proceedings of the Design, Automation and Test in Europe, 2010

Synchronization of washing operations with droplet routing for cross-contamination avoidance in digital microfluidic biochips.
Proceedings of the 47th Design Automation Conference, 2010

Testing of Low-Cost Digital Microfluidic Biochips with Non-regular Array Layouts.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

Optimization and Selection of Diagnosis-Oriented Fault-Insertion Points for System Test.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

A Noise-Aware Hybrid Method for SDD Pattern Grading and Selection.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

Testing of Digital Microfluidic Biochips Using Improved Eulerization Techniques and the Chinese Postman Problem.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

Defect Coverage-Driven Window-Based Test Compression.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

Circuit Topology-Based Test Pattern Generation for Small-Delay Defects.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

Mimicking of Functional State Space with Structural Tests for the Diagnosis of Board-Level Functional Failures.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

Digital Microfluidic Biochips - Design Automation and Optimization.
CRC Press, ISBN: 978-1-4398-1915-9, 2010

2009
Wafer-Level Defect Screening for "Big-D/Small-A" Mixed-Signal SoCs.
IEEE Trans. VLSI Syst., 2009

Power Management Using Test-Pattern Ordering for Wafer-Level Test During Burn-In.
IEEE Trans. VLSI Syst., 2009

SOC test-architecture optimization for the testing of embedded cores and signal-integrity faults on core-external interconnects.
ACM Trans. Design Autom. Electr. Syst., 2009

Deviation-Based LFSR Reseeding for Test-Data Compression.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

Integrated LFSR Reseeding, Test-Access Optimization, and Test Scheduling for Core-Based System-on-Chip.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

Test-Length and TAM Optimization for Wafer-Level Reduced Pin-Count Testing of Core-Based SoCs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling.
IEEE Trans. Computers, 2009

Fault Modeling and Functional Test Methods for Digital Microfluidic Biochips.
IEEE Trans. Biomed. Circuits and Systems, 2009

Guest Editorial - Selected Papers from the IEEE International Mixed-Signals, Sensors, and Systems Test Workshop (IMS3TW), 2008.
IEEE Trans. Biomed. Circuits and Systems, 2009

Scan-chain design and optimization for three-dimensional integrated circuits.
JETC, 2009

On-Line Testing of Lab-on-Chip Using Reconfigurable Digital-Microfluidic Compactors.
International Journal of Parallel Programming, 2009

Advances in nanoelectronics circuits and systems [Editorial].
IET Computers & Digital Techniques, 2009

Connecting fabrication defects to fault models and SPICE simulations for DNA self-assembled nanoelectronics.
IET Computers & Digital Techniques, 2009

Test Challenges for 3D Integrated Circuits.
IEEE Design & Test of Computers, 2009

Design-for-Testability for Digital Microfluidic Biochips.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

RT-Level Deviation-Based Grading of Functional Test Sequences.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Physical defect modeling for fault insertion in system reliability test.
Proceedings of the 2009 IEEE International Test Conference, 2009

Test-wrapper optimization for embedded cores in TSV-based three-dimensional SOCs.
Proceedings of the 27th International Conference on Computer Design, 2009

Testing bio-chips.
Proceedings of the 27th International Conference on Computer Design, 2009

Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

RTL DFT techniques to enhance defect coverage for functional test sequences.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2009

Dual-threshold pass-transistor logic design.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Cross-contamination avoidance for droplet routing in digital microfluidic biochips.
Proceedings of the Design, Automation and Test in Europe, 2009

Seed selection in LFSR-reseeding-based test compression for the detection of small-delay defects.
Proceedings of the Design, Automation and Test in Europe, 2009

Generation of compact test sets with high defect coverage.
Proceedings of the Design, Automation and Test in Europe, 2009

Diverse Routing: Exploiting Social Behavior for Routing in Delay-Tolerant Networks.
Proceedings of the 12th IEEE International Conference on Computational Science and Engineering, 2009

Compact Test Generation for Small-Delay Defects Using Testable-Path Information.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

Bit-Operation-Based Seed Augmentation for LFSR Reseeding with High Defect Coverage.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Test Data Compression Using Selective Encoding of Scan Slices.
IEEE Trans. VLSI Syst., 2008

Adaptive Cooling of Integrated Circuits Using Digital Microfluidics.
IEEE Trans. VLSI Syst., 2008

Power-aware SoC test planning for effective utilization of port-scalable testers.
ACM Trans. Design Autom. Electr. Syst., 2008

Introduction to joint ACM JETC/TODAES special issue on new, emerging, and specialized technologies.
ACM Trans. Design Autom. Electr. Syst., 2008

A Droplet-Manipulation Method for Achieving High-Throughput in Cross-Referencing-Based Digital Microfluidic Biochips.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

A Reconfigurable Scan Architecture With Weighted Scan-Enable Signals for Deterministic BIST.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Test-Quality/Cost Optimization Using Output-Deviation-Based Reordering of Test Patterns.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Cycle-Accurate Test Power Modeling and Its Application to SoC Test Architecture Design and Scheduling.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Defect-Aware High-Level Synthesis and Module Placement for Microfluidic Biochips.
IEEE Trans. Biomed. Circuits and Systems, 2008

Integrated droplet routing and defect tolerance in the synthesis of digital microfluidic biochips.
JETC, 2008

High-level synthesis of digital microfluidic biochips.
JETC, 2008

Introduction to DAC 2007 special section.
JETC, 2008

Introduction to joint ACM JETC/TODAES special issue on new, emerging, and specialized technologies.
JETC, 2008

Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips.
IEICE Transactions, 2008

A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction.
J. Electronic Testing, 2008

A Digital-Microfluidic Approach to Chip Cooling.
IEEE Design & Test of Computers, 2008

Test-Pattern Grading and Pattern Selection for Small-Delay Defects.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Test-Pattern Ordering for Wafer-Level Test-During-Burn-In.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Digital Microfluidic Logic Gates.
Proceedings of the Nano-Net - Third International ICST Conference, 2008

Built-in Self-Test and Fault Diagnosis for Lab-on-Chip Using Digital Microfluidic Logic Gates.
Proceedings of the 2008 IEEE International Test Conference, 2008

Interconnect-Aware and Layout-Oriented Test-Pattern Selection for Small-Delay Defects.
Proceedings of the 2008 IEEE International Test Conference, 2008

Test-Access Solutions for Three-Dimensional SOCs.
Proceedings of the 2008 IEEE International Test Conference, 2008

Fabrication Defects and Fault Models for DNA Self-Assembled Nanoelectronics.
Proceedings of the 2008 IEEE International Test Conference, 2008

SOC Test Optimization with Compression-Technique Selection.
Proceedings of the 2008 IEEE International Test Conference, 2008

Automated design of digital microfluidic lab-on-chip under pin-count constraints.
Proceedings of the 2008 International Symposium on Physical Design, 2008

On-Line Testing of Lab-on-Chip Using Digital Microfluidic Compactors.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

Test-access mechanism optimization for core-based three-dimensional SOCs.
Proceedings of the 26th International Conference on Computer Design, 2008

Design and optimization of a digital microfluidic biochip for protein crystallization.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns.
Proceedings of the Design, Automation and Test in Europe, 2008

Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs.
Proceedings of the Design, Automation and Test in Europe, 2008

Broadcast electrode-addressing for pin-constrained multi-functional digital microfluidic biochips.
Proceedings of the 45th Design Automation Conference, 2008

Accelerated Functional Testing of Digital Microfluidic Biochips.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

Core-Level Compression Technique Selection and SOC Test Architecture Design.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

Power Management for Wafer-Level Test During Burn-In.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007
Wafer-Level Modular Testing of Core-Based SoCs.
IEEE Trans. VLSI Syst., 2007

Scan-BIST based on cluster analysis and the encoding of repeating sequences.
ACM Trans. Design Autom. Electr. Syst., 2007

Distributed Mobility Management for Target Tracking in Mobile Sensor Networks.
IEEE Trans. Mob. Comput., 2007

Test Wrapper Design and Optimization Under Power Constraints for Embedded Cores With Multiple Clock Domains.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Optimization of Dual-Speed TAM Architectures for Efficient Modular Testing of SOCs.
IEEE Trans. Computers, 2007

Parallel Scan-Like Test and Multiple-Defect Diagnosis for Digital Microfluidic Biochips.
IEEE Trans. Biomed. Circuits and Systems, 2007

Automated design of pin-constrained digital microfluidic biochips under droplet-interference constraints.
JETC, 2007

Editorial to special issue DAC 2006.
JETC, 2007

Redundancy Analysis and a Distributed Self-Organization Protocol for Fault-Tolerant Wireless Sensor Networks.
IJDSN, 2007

Built-in Self-test and Defect Tolerance in Molecular Electronics-based Nanofabrics.
J. Electronic Testing, 2007

Testing and Diagnosis of Realistic Defects in Digital Microfluidic Biochips.
J. Electronic Testing, 2007

Guest Editors' Introduction: Biochips and Integrated Biosensor Platforms.
IEEE Design & Test of Computers, 2007

Rapid Generation of Thermal-Safe Test Schedules
CoRR, 2007

Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores
CoRR, 2007

Design of Fault-Tolerant and Dynamically-Reconfigurable Microfluidic Biochips
CoRR, 2007

Yield Enhancement of Digital Microfluidics-Based Biochips Using Space Redundancy and Local Reconfiguration
CoRR, 2007

Defect-Aware Synthesis of Droplet-Based Microfluidic Biochips.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

An ECO Technique for Removing Crosstalk Violations in Clock Networks.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Test-Length Selection and TAM Optimization for Wafer-Level, Reduced Pin-Count Testing of Core-Based Digital SoCs.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Privacy-Preserving Detection of Sybil Attacks in Vehicular Ad Hoc Networks.
Proceedings of the 4th Annual International Conference on Mobile and Ubiquitous Systems (MobiQuitous 2007), 2007

Test-wrapper designs for the detection of signal-integrity faults on core-external interconnects of SoCs.
Proceedings of the 2007 IEEE International Test Conference, 2007

Functional testing of digital microfluidic biochips.
Proceedings of the 2007 IEEE International Test Conference, 2007

Parallel Scan-Like Testing and Fault Diagnosis Techniques for Digital Microfluidic Biochips.
Proceedings of the 12th European Test Symposium, 2007

A Seed-Selection Method to Increase Defect Coverage for LFSR-Reseeding-Based Test Compression.
Proceedings of the 12th European Test Symposium, 2007

Design and Test of Microfluidic Biochips.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

A cross-referencing-based droplet manipulation method for high-throughput and pin-constrained digital microfluidic arrays.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

SoC testing using LFSR reseeding, and scan-slice-based TAM optimization and test scheduling.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Heterogeneous systems on chip and systems in package.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

SOC Test Architecture Optimization for Signal Integrity Faults on Core-External Interconnects.
Proceedings of the 44th Design Automation Conference, 2007

Integrated Droplet Routing in the Synthesis of Microfluidic Biochips.
Proceedings of the 44th Design Automation Conference, 2007

AWafer-Level Defect Screening Technique to Reduce Test and Packaging Costs for "Big-D/Small-A" Mixed-Signal SoCs.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Digital Microfluidic Biochips - Synthesis, Testing, and Reconfiguration Techniques.
CRC Press, ISBN: 978-0-8493-9009-8, 2007

2006
Test infrastructure design for mixed-signal SOCs with wrapped analog cores.
IEEE Trans. VLSI Syst., 2006

Concurrent testing of digital microfluidics-based biochips.
ACM Trans. Design Autom. Electr. Syst., 2006

Module placement for fault-tolerant microfluidics-based biochips.
ACM Trans. Design Autom. Electr. Syst., 2006

A unified approach for fault tolerance and dynamic power management in fixed-priority real-time embedded systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Microfluidics-Based Biochips: Technology Issues, Implementation Platforms, and Design-Automation Challenges.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Defect Tolerance Based on Graceful Degradation and Dynamic Reconfiguration for Digital Microfluidics-Based Biochips.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Thermal-Safe Test Scheduling for Core-Based System-on-Chip Integrated Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Yield enhancement of reconfigurable microfluidics-based biochips using interstitial redundancy.
JETC, 2006

Test Planning and Test Resource Optimization for Droplet-Based Microfluidic Systems.
J. Electronic Testing, 2006

Authentication of sensor network flooding based on neighborhood cooperation.
Proceedings of the IEEE Wireless Communications and Networking Conference, 2006

Cycle-Accurate Test Power Modeling and its Application to SoC Test Scheduling.
Proceedings of the 2006 IEEE International Test Conference, 2006

Defect-Oriented and Time-Constrained Wafer-Level Test-Length Selection for Core-Based Digital SoCs.
Proceedings of the 2006 IEEE International Test Conference, 2006

Automated Design of Microfluidics-Based Biochips: Connecting Biochemistry to Electronics CAD.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

An evaluation of the impact of gate oxide tunneling on dual-Vt-based leakage reduction techniques.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Reconfiguration-Based Defect Tolerance for Microfluidic Biochips.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

Test set enrichment using a probabilistic fault model and the theory of output deviations.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Droplet routing in the synthesis of digital microfluidic biochips.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Hierarchy-aware and area-efficient test infrastructure design for core-based system chips.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Automated design of pin-constrained digital microfluidic arrays for lab-on-a-chip applications*.
Proceedings of the 43rd Design Automation Conference, 2006

Droplet-trace-based array partitioning and a pin assignment algorithm for the automated design of digital microfluidic biochips.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

2005
Modular Testing and Built-In Self-Test of Embedded Cores in System-on-Chip Integrated Circuits.
Proceedings of the Embedded Systems Handbook., 2005

Nine-coded compression technique for testing embedded cores in SoCs.
IEEE Trans. VLSI Syst., 2005

Design and analysis of compact dictionaries for diagnosis in scan-BIST.
IEEE Trans. VLSI Syst., 2005

Computing reliability and message delay for Cooperative wireless distributed sensor networks subject to random failures.
IEEE Trans. Reliability, 2005

Pruning-based, energy-optimal, deterministic I/O device scheduling for hard real-time systems.
ACM Trans. Embedded Comput. Syst., 2005

Test planning for modular testing of hierarchical SOCs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

A Distributed Coverage- and Connectivity-Centric Technique for Selecting Active Nodes in Wireless Sensor Networks.
IEEE Trans. Computers, 2005

Location-Aided Flooding: An Energy-Efficient Data Dissemination Protocol for Wireless Sensor Networks.
IEEE Trans. Computers, 2005

Design automation for microfluidics-based biochips.
JETC, 2005

Defect Tolerance for Gracefully-Degradable Microfluidics-Based Biochips.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Design, Testing, and Applications of Digital Microfluidics-Based Biochips.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Test data compression for IP embedded cores using selective encoding of scan slices.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Using built-in self-test and adaptive recovery for defect tolerance in molecular electronics-based nanofabrics.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Defect-oriented testing and diagnosis of digital microfluidics-based biochips.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

A Flexible Design Methodology for Analog Test Wrappers in Mixed-Signal SOCs.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Test planning for the effective utilization of port-scalable testers for heterogeneous core-based SOCs.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

A cocktail approach on random access scan toward low power and high efficiency test.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Built-in self-test of molecular electronics-based nanofabrics.
Proceedings of the 10th European Test Symposium, ETS 2005, Tallinn, 2005

Improving Thermal-Safe Test Scheduling for Core-Based Systems-on-Chip Using Shift Frequency Scaling.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

Fault-Tolerant Self-organization in Sensor Networks.
Proceedings of the Distributed Computing in Sensor Systems, 2005

Yield Enhancement of Digital Microfluidics-Based Biochips Using Space Redundancy and Local Reconfiguration.
Proceedings of the 2005 Design, 2005

Design of Fault-Tolerant and Dynamically-Reconfigurable Microfluidic Biochips.
Proceedings of the 2005 Design, 2005

Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores.
Proceedings of the 2005 Design, 2005

Rapid Generation of Thermal-Safe Test Schedules.
Proceedings of the 2005 Design, 2005

Hybrid BIST Based on Repeating Sequences and Cluster Analysis.
Proceedings of the 2005 Design, 2005

Multi-frequency wrapper design and optimization for embedded cores under average power constraints.
Proceedings of the 42nd Design Automation Conference, 2005

Unified high-level synthesis and module placement for defect-tolerant microfluidic biochips.
Proceedings of the 42nd Design Automation Conference, 2005

System-level design automation tools for digital microfluidic biochips.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Advances in Target Tracking and Active Surveillance Using Wireless Sensor Networks.
Proceedings of the Handbook on Theoretical and Algorithmic Aspects of Sensor, 2005

Scalable infrastructure for distributed sensor networks.
Springer, ISBN: 978-1-85233-951-7, 2005

2004
SOC test planning using virtual test access architectures.
IEEE Trans. VLSI Syst., 2004

On Computing Mobile Agent Routes for Data Fusion in Distributed Sensor Networks.
IEEE Trans. Knowl. Data Eng., 2004

Sensor deployment and target localization in distributed sensor networks.
ACM Trans. Embedded Comput. Syst., 2004

Dynamic adaptation for fault tolerance and power management in embedded real-time systems.
ACM Trans. Embedded Comput. Syst., 2004

Behavioral modeling and performance evaluation of microelectrofluidics-based PCR systems using SystemC.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

Network flow techniques for dynamic voltage scaling in hard real-time systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

Identification of error-capturing scan cells in scan-BIST with applications to system-on-chip.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

Test set embedding for deterministic BIST using a reconfigurable interconnection network.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

Compact Dictionaries for Fault Diagnosis in Scan-BIST.
IEEE Trans. Computers, 2004

Uncertainty-aware and coverage-oriented deployment for sensor networks.
J. Parallel Distrib. Comput., 2004

On Using Exponential-Golomb Codes and Subexponential Codes for System-on-a-Chip Test Data Compression.
J. Electronic Testing, 2004

A Signature Analysis Technique for the Identification of Failing Vectors with Application to Scan-BIST.
J. Electronic Testing, 2004

Analysis of Test Application Time for Test Data Compression Methods Based on Compression Codes.
J. Electronic Testing, 2004

Concurrent Testing of Droplet-Based Microfluidic Systems for Multiplexed Biomedical Assays.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

IEEE P1500-Compliant Test Wrapper Design for Hierarchical Cores.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Compact Dictionaries for Diagnosis of Unmodeled Faults in Scan-BIST.
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

Architectural-level synthesis of digital microfluidics-based biochips.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Test planning and test resource optimization for droplet-based microfluidic systems.
Proceedings of the 9th European Test Symposium, 2004

Task Feasibility Analysis and Dynamic Voltage Scaling in Fault-Tolerant Real-Time Embedded Systems.
Proceedings of the 2004 Design, 2004

Nine-Coded Compression Technique with Application to Reduced Pin-Count Testing and Flexible On-Chip Decompression.
Proceedings of the 2004 Design, 2004

Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures.
Proceedings of the 2004 Design, 2004

Energy-aware deterministic fault tolerance in distributed real-time embedded systems.
Proceedings of the 41th Design Automation Conference, 2004

2003
A synthesis-for-transparency approach for hierarchical and system-on-a-chip test.
IEEE Trans. VLSI Syst., 2003

Test data compression using dictionaries with selective entries and fixed-length indices.
ACM Trans. Design Autom. Electr. Syst., 2003

Parity bit signature in response data compaction and built-in self-testing of VLSI circuits with nonexhaustive test sets.
IEEE Trans. Instrumentation and Measurement, 2003

Space compaction of test responses using orthogonal transmission functions [logic testing].
IEEE Trans. Instrumentation and Measurement, 2003

Energy-conscious, deterministic I/O device scheduling in hard real-time systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Failing vector identification based on overlapping intervals of test vectors in a scan-BIST environment.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Efficient test access mechanism optimization for system-on-chip.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

A unified approach to reduce SOC test data volume, scan power and testing time.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip.
IEEE Trans. Computers, 2003

Test Data Compression and Test Resource Partitioning for System-on-a-Chip Using Frequency-Directed Run-Length (FDR) Codes.
IEEE Trans. Computers, 2003

Target localization based on energy considerations in distributed sensor networks.
Ad Hoc Networks, 2003

Sensor placement for effective coverage and surveillance in distributed sensor networks.
Proceedings of the 2003 IEEE Wireless Communications and Networking, 2003

Test Data Compression Using Dictionaries with Fixed-Length Indices.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Design and Optimization of Multi-level TAM Architectures for Hierarchical SOCs.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Energy-Aware Target Localization in Wireless Sensor Networks.
Proceedings of the First IEEE International Conference on Pervasive Computing and Communications (PerCom'03), 2003

Testing of Droplet-Based Microelectrofluidic Systems.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Deterministic BIST Based on a Reconfigurable Interconnection Network.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Compact Dictionaries for Fault Diagnosis in BIST.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

Sensor Deployment and Target Localization Based on Virtual Forces.
Proceedings of the Proceedings IEEE INFOCOM 2003, The 22nd Annual Joint Conference of the IEEE Computer and Communications Societies, San Franciso, CA, USA, March 30, 2003

On Combining Pinpoint Test Set Relaxation and Run-Length Codes for Reducing Test Data Volume.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Energy-Aware Fault Tolerance in Fixed-Priority Real-Time Embedded Systems.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Generalized Network Flow Techniques for Dynamic Voltage Scaling in Hard Real-Time Systems.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

TAM Optimization for Mixed-Signal SOCs using Analog Test Wrappers.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Cooling of integrated circuits using droplet-based microfluidics.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

Uncertainty-aware sensor deployment algorithms for surveillance applications.
Proceedings of the Global Telecommunications Conference, 2003

Fault Recovery Based on Checkpointing for Hard Real-Time Embedded Systems.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

Energy-Aware Adaptive Checkpointing in Embedded Real-Time Systems.
Proceedings of the 2003 Design, 2003

EBIST: A Novel Test Generator with Built-In Fault Detection Capability.
Proceedings of the 2003 Design, 2003

A Partition-Based Approach for Identifying Failing Scan Cells in Scan-BIST with Applications to System-on-Chip Fault Diagnosis.
Proceedings of the 2003 Design, 2003

A Unified Approach for SOC Testing Using Test Data Compression and TAM Optimization.
Proceedings of the 2003 Design, 2003

Test cost reduction for SOCs using virtual TAMs and lagrange multipliers.
Proceedings of the 40th Design Automation Conference, 2003

Adaptive Checkpointing with Dynamic Voltage Scaling in Embedded Real-Time Systems.
Proceedings of the Embedded Software for SoC, 2003

2002
Data compression in space under generalized mergeability based on concepts of cover table and frequency ordering.
IEEE Trans. Instrumentation and Measurement, 2002

Design of reconfigurable composite microsystems based on hardware/software codesign principles.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

Test data compression and decompression based on internal scanchains and Golomb coding.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

Low-power scan testing and test data compression forsystem-on-a-chip.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

Synthesis of single-output space compactors for scan-based sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

Test Bus Sizing for System-on-a-Chip.
IEEE Trans. Computers, 2002

Grid Coverage for Surveillance and Target Location in Distributed Sensor Networks.
IEEE Trans. Computers, 2002

High Performance Sensor Integration in Distributed Sensor Networks Using Mobile Agents.
IJHPCA, 2002

Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip.
J. Electronic Testing, 2002

Guest Editorial.
J. Electronic Testing, 2002

How Useful are the ITC 02 SoC Test Benchmarks?
IEEE Design & Test of Computers, 2002

On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

How Effective are Compression Codes for Reducing Test Data Volume?
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Experiences in Implementing an Energy-Driven Task Scheduler in RT-Linux.
Proceedings of the 8th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2002), 2002

A Set of Benchmarks fo Modular Testing of SOCs.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Test Resource Optimization for Multi-Site Testing of SOCs Under ATE Memory Depth Constraints.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

An Interval-Based Diagnosis Scheme for Identifying Failing Vectors in a Scan-BIST Environment.
Proceedings of the 2002 Design, 2002

Efficient Wrapper/TAM Co-Optimization for Large SOCs.
Proceedings of the 2002 Design, 2002

Test Resource Partitioning and Reduced Pin-Count Testing Based on Test Data Compression.
Proceedings of the 2002 Design, 2002

Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs.
Proceedings of the 39th Design Automation Conference, 2002

Reduction of SOC test data volume, scan power and testing time using alternating run-length codes.
Proceedings of the 39th Design Automation Conference, 2002

Pruning-based energy-optimal device scheduling for hard real-time systems.
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002

Recent Advances in Test Planning for Modular Testing of Core-Based SOCs.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

Robust Space Compaction of Test Responses.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

Test Resource Partitioning for System-on-a-Chip.
Frontiers in electronic testing 20, Kluwer / Springer, ISBN: 978-1-4020-7119-5, 2002

2001
Efficient Test Application for Core-Based Systems Using Twisted-Ring Counters.
VLSI Design, 2001

Multiresolution data integration using mobile agents in distributed sensor networks.
IEEE Trans. Systems, Man, and Cybernetics, Part C, 2001

Optimal test access architectures for system-on-a-chip.
ACM Trans. Design Autom. Electr. Syst., 2001

Scheduling of microfluidic operations for reconfigurabletwo-dimensional electrowetting arrays.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

System-on-a-chip test-data compression and decompressionarchitectures based on Golomb codes.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Real-time task scheduling for energy-aware embedded systems.
J. Franklin Institute, 2001

Distributed sensor networks - a review of recent research.
J. Franklin Institute, 2001

On Using Twisted-Ring Counters for Test Set Embedding in BIST.
J. Electronic Testing, 2001

Test Resource Partitioning for SOCs.
IEEE Design & Test of Computers, 2001

Design of Parameterizable Error-Propagating Space Compactors for Response Observation.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-Chip.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Frequency-Directed Run-Length (FDR) Codes with Application to System-on-a-Chip Test Data Compression.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Synthesis Of Transparent Circuits For Hierarchical An System-On-A-Chip Test.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Coding Theory Framework for Target Location in Distributed Sensor Networks.
Proceedings of the 2001 International Symposium on Information Technology (ITCC 2001), 2001

Test wrapper and test access mechanism co-optimization for system-on-chip.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Efficient test data compression and decompression for system-on-a-chip using internal scan chains and Golomb coding.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Combining Low-Power Scan Testing and Test Data Compression for System-on-a-Chip.
Proceedings of the 38th Design Automation Conference, 2001

Dynamic I/O power management for hard real-time systems.
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001

Investigating the effect of voltage-switching on low-energy task scheduling in hard real-time systems.
Proceedings of ASP-DAC 2001, 2001

Synthesis of single-output space compactors with application to scan-based IP cores.
Proceedings of ASP-DAC 2001, 2001

2000
Deterministic built-in test pattern generation for high-performance circuits using twisted-ring counters.
IEEE Trans. VLSI Syst., 2000

Space compression revisited.
IEEE Trans. Instrumentation and Measurement, 2000

Test-set embedding based on width compression for mixed-mode BIST.
IEEE Trans. Instrumentation and Measurement, 2000

Test scheduling for core-based systems using mixed-integer linearprogramming.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

Space Compaction of Test Responses for IP Cores Using Orthogonal Transmission Functions.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Test Data Compression for System-on-a-Chip Using Golomb Codes.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Design of System-on-a-Chip Test Access Architectures using Integer Linear Programming.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Mathematical Modeling of Intellectual Property Protection Using Partially-Mergeable Cores.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000

Built-in self testing of high-performance circuits using twisted-ring counters.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Design of system-on-a-chip test access architectures under place-and-route and power constraints.
Proceedings of the 37th Conference on Design Automation, 2000

1999
On the Covering of Vertices for Fault Diagnosis in Hypercubes.
Inf. Process. Lett., 1999

Deterministic Built-in Pattern Generation for Sequential Circuits.
J. Electronic Testing, 1999

Built-in Test Pattern Generation For High-Performance Cir cuits Using Twisted-Ring Counters.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Test pattern generation for width compression in BIST.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Test scheduling for core-based systems.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

1998
Zero-aliasing space compaction of test responses using multiple parity signatures.
IEEE Trans. VLSI Syst., 1998

On a New Class of Codes for Identifying Vertices in Graphs.
IEEE Trans. Information Theory, 1998

Huffman encoding of test sets for sequential circuits.
IEEE Trans. Instrumentation and Measurement, 1998

Design of built-in test generator circuits using width compression.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

Zero-aliasing space compaction using linear compactors with bounded overhead.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

Optimal Zero-Aliasing Space Compaction of Test Responses.
IEEE Trans. Computers, 1998

Built-In Self Testing of Sequential Circuits Using Precomputed Test Sets.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

1997
On the quality of accumulator-based compaction of test responses.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

An Efficient Finite-State Machine Implementation of Huffman Decoders.
Inf. Process. Lett., 1997

Test Width Compression for Built-In Self Testing.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

1996
Test response compaction using multiplexed parity trees.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1996

Balance testing and balance-testable design of logic circuits.
J. Electronic Testing, 1996

1995
Cumulative balance testing of logic circuits.
IEEE Trans. VLSI Syst., 1995

Optimal Space Compaction of Test Responses.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

1994
Efficient Test-Response Compression for Multiple-Output Cicuits.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

DFBT: A Design-for-Testability Method Based on Balance Testing.
Proceedings of the 31st Conference on Design Automation, 1994

1993
Aliasing-free error detection (ALFRED).
Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993

Balance Testing of Logic Circuits.
Proceedings of the Digest of Papers: FTCS-23, 1993


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