Brett Feero

According to our database, Brett Feero authored at least 5 papers between 2006 and 2011.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2011

Three-Dimensional Networks-on-Chip: Performance Evaluation.

Brett Stanley Feero, Partha Pratim Pande

Proceedings of the 3D Integration for NoC-based SoC Architectures, 2011

2009

Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation.

Brett Feero, Partha Pratim Pande

IEEE Trans. Computers, 2009

2007

Performance Evaluation for Three-Dimensional Networks-On-Chip.

Brett Feero, Partha Pratim Pande

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Applicability of Energy Efficient Coding Methodology to Address Signal Integrity in 3D NoC Fabrics.

Partha Pratim Pande, Amlan Ganguly, Brett Feero, Cristian Grecu

Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

2006

Design of Low power & Reliable Networks on Chip through joint crosstalk avoidance and forward error correction coding.

Partha Pratim Pande, Amlan Ganguly, Brett Feero, Benjamin Belzer, Cristian Grecu

Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006