Cristian Grecu

According to our database1, Cristian Grecu authored at least 31 papers between 2003 and 2014.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2014
A novel tri-state device implemented with a metal gated QCA.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

2011
Challenges and promises of nano and bio communication networks.
Proceedings of the NOCS 2011, 2011

2009
Application modelling and hardware description for network-on-chip benchmarking.
IET Comput. Digit. Tech., 2009

2008
An FPGA Design Project: Creating a PowerPC Subsystem Plus User Logic.
IEEE Trans. Educ., 2008

Energy reduction through crosstalk avoidance coding in networks on chip.
J. Syst. Archit., 2008

Design of Low Power & Reliable Networks on Chip Through Joint Crosstalk Avoidance and Multiple Error Correction Coding.
J. Electron. Test., 2008

Improving the scalability of checkpoint recovery for networks-on-chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Communication Aware Recovery Configurations for Networks-on-Chip.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

Coordinated versus Uncoordinated Checkpoint Recovery for Network-on-Chip Based Systems.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

2007
Testing Network-on-Chip Communication Fabrics.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Towards Open Network-on-Chip Benchmarks.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

Addressing Signal Integrity in Networks on Chip Interconnects through Crosstalk-Aware Double Error Correction Coding.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Applicability of Energy Efficient Coding Methodology to Address Signal Integrity in 3D NoC Fabrics.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Essential Fault-Tolerance Metrics for NoC Infrastructures.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Performance Evaluation of Adaptive Routing Algorithms for achieving Fault Tolerance in NoC Fabrics.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

2006
System-on-Chip: Reuse and Integration.
Proc. IEEE, 2006

BIST for Network-on-Chip Interconnect Infrastructures.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Crosstalk-aware Energy Reduction in NoC Communication Fabrics.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

On-line Fault Detection and Location for NoC Interconnects.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

Energy Reduction through Crosstalk Avoidance Coding in NoC Paradigm.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

Design of Low power & Reliable Networks on Chip through joint crosstalk avoidance and forward error correction coding.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

NoC Interconnect Yield Improvement Using Crosspoint Redundancy.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

2005
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures.
IEEE Trans. Computers, 2005

Timing analysis of network on chip architectures for MP-SoC platforms.
Microelectron. J., 2005

Design, Synthesis, and Test of Networks on Chips.
IEEE Des. Test Comput., 2005

Effect of traffic localization on energy dissipation in NoC-based interconnect.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Methodologies and Algorithms for Testing Switch-Based NoC Interconnects.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

2004
A Scalable Communication-Centric SoC Interconnect Architecture.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

2003
High-Throughput Switch-Based Interconnect for Future SoCs.
Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June, 2003

Design of a switch for network on chip applications.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003


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