Bupesh Pandita

According to our database, Bupesh Pandita authored at least 6 papers between 1999 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2023

Reference Clock Jitter Immunity by Accurate DPLL Bandwidth Control in a Multiple-link Die-to-Die Interface.

Ping Lu, Bupesh Pandita, Minhan Chen

Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

2022

A Low-Ripple Resistor-Less Hybrid Loop Filter based PLL in 3nm FinFET.

Ping Lu, Charlie Boecker, Bupesh Pandita, Minhan Chen, Sheethal Nayak

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2015

Delay calibration circuit for delay lines.

Bupesh Pandita

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2009

Oversampling A/D Converters With Reduced Sensitivity to DAC Nonlinearities.

Bupesh Pandita, Kenneth W. Martin

IEEE Trans. Circuits Syst. II Express Briefs, 2009

2007

Designing Complex Delta Sigma Modulators with Signal-Transfer Functions having Good Stop-Band Attenuation.

Bupesh Pandita, Kenneth W. Martin

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

1999

Design and Implementation of Viterbi Decoder Using FPGAs.

Bupesh Pandita, Subir K. Roy

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999