Subir K. Roy

Orcid: 0000-0002-3554-1312

According to our database1, Subir K. Roy authored at least 14 papers between 1993 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2016
An efficient FPGA-based function profiler for embedded system applications.
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

Formal verification of switched capacitor DC to DC power converter using circuit simulation traces.
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

2013
Formal Verification of Analog and Mixed Signal Designs Using SPICE Circuit Simulation Traces.
J. Electron. Test., 2013

2010
DFT logic verification through property based formal methods - SOC to IP.
Proceedings of 10th International Conference on Formal Methods in Computer-Aided Design, 2010

2008
Verification of a MEMS based adaptive cruise control system using simulation and semi-formal approaches.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007
Modeling Techniques for Formal Verification of BIST Controllers and Their Integration into SOC Designs.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Top Level SOC Interconnectivity Verification Using Formal Techniques.
Proceedings of the Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), 2007

2002
Functional Verification of System on Chips-Practices, Issues and Challenges (Tutorial Abstract).
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

2000
Dataflow Analysis for Resource Contention and Register Leakage Properties.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Formal verification based on assume and guarantee approach - a case study (short paper).
Proceedings of ASP-DAC 2000, 2000

1999
Design and Implementation of Viterbi Decoder Using FPGAs.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

TECHMIG: A Layout Tool for Technology Migration.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

1996
Approximation Algorithms for Min-k-Overlap Problems Using the Principal Lattice of Partitions Approach.
J. Algorithms, 1996

1993
Application of the principal partition and principal lattice of partitions of a graph to the problem of decomposition of a finite state machine.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993


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