Byeong Kil Lee

According to our database1, Byeong Kil Lee authored at least 22 papers between 2002 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
Implications for Hardware Acceleration of Malware Detection.
Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

2014
Performance enhancement in shared-memory multiprocessors using dynamically classified sharing information.
Proceedings of the IEEE 33rd International Performance Computing and Communications Conference, 2014

2013
Proposed enhancements to fixed segmented LRU cache replacement policy.
Proceedings of the IEEE 32nd International Performance Computing and Communications Conference, 2013

2012
Reducing thermal hotspots in microprocessors with expanded component sizing.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

Performance-Sensitivity-based Workload Tailoring for Effective Design Exploration.
Proceedings of the Ninth International Conference on Information Technology: New Generations, 2012

Performance hotspot based CUDA acceleration.
Proceedings of the International SoC Design Conference, 2012

AES decryption using warp-synchronous programming.
Proceedings of the 31st IEEE International Performance Computing and Communications Conference, 2012

Fixed Segmented LRU cache replacement scheme with selective caching.
Proceedings of the 31st IEEE International Performance Computing and Communications Conference, 2012

Performance-sensitivity and performance-similarity based workload reduction.
Proceedings of the 31st IEEE International Performance Computing and Communications Conference, 2012

2011
Hybrid-way Cache for Mobile Processors.
Proceedings of the Eighth International Conference on Information Technology: New Generations, 2011

CUDA acceleration of P7Viterbi algorithm in HMMER 3.0.
Proceedings of the 30th IEEE International Performance Computing and Communications Conference, 2011

2010
Way-load balancing scheme for mobile cache LRU replacement.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Composite Pseudo-Associative Cache for Mobile Processors.
Proceedings of the MASCOTS 2010, 2010

Towards Smaller-Sized Cache for Mobile Processors Using Shared Set-Associativity.
Proceedings of the Seventh International Conference on Information Technology: New Generations, 2010

Architectural Sensitivity Analysis on Network Workloads.
Proceedings of the 2010 International Conference on Computer Design, 2010

Leakage and Access Time Tradeoffs for Cache in High Performance Microprocessors.
Proceedings of the 2010 International Conference on Computer Design, 2010

2009
Hardware Acceleration for Media/Transaction Applications in Network Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2009

2006
Architectural enhancements for network congestion control applications.
IEEE Trans. Very Large Scale Integr. Syst., 2006

2005
Implications of Executing Compression and Encryption Applications on General Purpose Processors.
IEEE Trans. Computers, 2005

Architectural Support for Accelerating Congestion Control Applications in Network Processors.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2003
NpBench: A Benchmark Suite for Control plane and Data plane Applications for Network Processors.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

2002
Implications of Programmable General Purpose Processors for Compression/Encryption Applications.
Proceedings of the 13th IEEE International Conference on Application-Specific Systems, 2002


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