Eugene John

According to our database1, Eugene John authored at least 56 papers between 1992 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

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Bibliography

2020
An Asynchronous High-Performance Approximate Adder with Low-Cost Error Correction.
J. Inf. Sci. Eng., 2020

2019
Design and Implementation of an Ultralow-Energy FFT ASIC for Processing ECG in Cardiac Pacemakers.
IEEE Trans. VLSI Syst., 2019

Resource Shared Galois Field Computation for Energy Efficient AES/CRC in IoT Applications.
T-SUSC, 2019

Wasted dynamic power and correlation to instruction set architecture for CPU throttling.
The Journal of Supercomputing, 2019

A metric for measuring power efficiency and data throughput in mobile ad hoc networks.
IJPEDS, 2019

Demystifying the MLPerf Benchmark Suite.
CoRR, 2019

A Study of Core Utilization and Residency in Heterogeneous Smart Phone Architectures.
Proceedings of the 2019 ACM/SPEC International Conference on Performance Engineering, 2019

Instruction Profiling Based Fetch Throttling for Wasted Dynamic Power Reduction.
Proceedings of the 31st International Symposium on Computer Architecture and High Performance Computing, 2019

Low-Power Advanced Encryption Standard for Implantable Cardiac Devices.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

2018
Performance Tradeoffs in the Design of Low-Power SRAM Arrays for Implantable Devices.
J. Low Power Electronics, 2018

Using Static Hardware Wrappers to Thwart Hardware Trojans and Code Bugs at Runtime.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Performance Analysis of Single-Precision Floating-Point MAC for Deep Learning.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

2017
FlowPaP and FlowReR: Improving Energy Efficiency and Performance for STT-MRAM-Based Handheld Devices under Read Disturbance.
ACM Trans. Embedded Comput. Syst., 2017

2016
Reducing Power and Cycle Requirement for Fast Fourier Transform of Electrocardiogram Signals Through Low Level Arithmetic Optimizations for Cardiac Implantable Devices.
J. Low Power Electronics, 2016

An Ultra-Low Power Charge Redistribution Successive Approximation Register A/D Converter for Biomedical Applications.
J. Low Power Electronics, 2016

Building trust in 3PIP using asset-based security property verification.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

2015
Time Series Forecasting of Cloud Data Center Workloads for Dynamic Resource Provisioning.
JoWUA, 2015

A Thermal-Aware Scheduling Algorithm for Core Migration in Multicore Processors.
J. Low Power Electronics, 2015

Securing Implantable Cardioverter Defibrillators Using Smartphones.
J. Internet Serv. Inf. Secur., 2015

Analysis of Memory Sensitive SPEC CPU2006 Integer Benchmarks for Big Data Benchmarking.
Proceedings of the 1st Workshop on Performance Analysis of Big Data Systems, 2015

2014
Autonomous control of issue queue utilization for simultaneous multi-threading processors.
Proceedings of the 2014 Spring Simulation Multiconference, 2014

Performance enhancement in shared-memory multiprocessors using dynamically classified sharing information.
Proceedings of the IEEE 33rd International Performance Computing and Communications Conference, 2014

2012
Probability-Based Optimal Sizing of Power-Gating Transistors in Full Adders for Reduced Leakage and High Performance.
J. Low Power Electronics, 2012

Adaptive instruction dispatching techniques for Simultaneous Multi-Threading (SMT) processors.
Comput. Electr. Eng., 2012

Performance-sensitivity and performance-similarity based workload reduction.
Proceedings of the 31st IEEE International Performance Computing and Communications Conference, 2012

2011
Execution characteristics of embedded applications on a Pentium 4-based personal computer.
J. Embedded Computing, 2011

2010
Impact of Operating System Behavior on Battery Life.
J. Low Power Electronics, 2010

Architectural Sensitivity Analysis on Network Workloads.
Proceedings of the 2010 International Conference on Computer Design, 2010

Leakage and Access Time Tradeoffs for Cache in High Performance Microprocessors.
Proceedings of the 2010 International Conference on Computer Design, 2010

Leakage Power Analysis of Multi-bit Adders Using Transistor Gate Length Increase.
Proceedings of the 2010 International Conference on Computer Design, 2010

2009
Implications of gated-Vss technique on leakage power in embedded caches.
IJES, 2009

Performance of commercial multimedia workloads on the Intel Pentium 4: A case study.
Comput. Electr. Eng., 2009

A Tale of Two Processors: Revisiting the RISC-CISC Debate.
Proceedings of the Computer Performance Evaluation and Benchmarking, 2009

Performance Measurement of Single, Dual and Quad Core Machines Using SPEC CPU2006.
Proceedings of the 2009 International Conference on Computer Design, 2009

2008
Caches for Multimedia Workloads: Power and Energy Tradeoffs.
IEEE Trans. Multimedia, 2008

A superscalar simulation employing poisson distributed stalls.
Comput. Electr. Eng., 2008

Energy Efficiency of Data Compression with Wavelets.
Proceedings of the 2008 International Conference on Image Processing, 2008

Effects of Register File Organization on Leakage Power Consumption.
Proceedings of the 2008 International Conference on Computer Design, 2008

Topology-related effects of Gated-Vdd and Gated-Vss techniques on full-adder leakage and delay at 65nm and 45 nm.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

Energy efficient lossless image compression with prediction-based transform.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
Static Power Analysis and Estimation in Ternary Content Addressable Memory Cells.
J. Low Power Electronics, 2007

Analysing the performance of personal computers based on Intel microprocessors for sequence aligning bioinformatics applications.
IJBRA, 2007

Performance Analysis of an Intel Pentium-4 Based Personal Computer for Multiplke Sequence Alignment.
Proceedings of the 2007 International Conference on Computer Design, 2007

2006
Architectural enhancements for network congestion control applications.
IEEE Trans. VLSI Syst., 2006

Performance Analysis of Embedded Applications on a Pentium-4 Based Machine.
Proceedings of the 2006 International Conference on Embedded Systems & Applications, 2006

Performance of Sequence Alignment Bioinformatics Applications on General Purpose Processors: A Case Study.
Proceedings of the 2006 International Conference on Bioinformatics & Computational Biology, 2006

2005
Implementation of Low Power Digital Multipliers using 10 -Transistor Adder Blocks.
J. Low Power Electronics, 2005

Parametrical characterization of leakage power in embedded system caches using gated-VSS.
Proceedings of the Third IASTED International Conference on Circuits, 2005

Architectural Support for Accelerating Congestion Control Applications in Network Processors.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004
Impact of nanotechnology on the performance of CMOS digital multipliers.
Proceedings of the Second IASTED International Conference on Circuits, 2004

2002
Cache performance of video computation workloads.
Proceedings of the Third International Workshop on Digital and Computational Video, 2002

1999
A flexible design for timing signals generation for the conversion of computer video formats to SDTV 480P.
IEEE Trans. Consumer Electronics, 1999

A Novel Low Power Energy Recovery Full Adder Cell.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

1998
Hybrid Tree: A Scalable Optoelectronic Interconnection Network for Parallel Computing.
Proceedings of the Thirty-First Annual Hawaii International Conference on System Sciences, 1998

1995
Design of a highly reconfigurable interconnect for array processors.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

1992
Design and VLSI implementation of an access processor for a decoupled architecture.
Microprocessors and Microsystems - Embedded Hardware Design, 1992


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