Savithra Eratne

According to our database, Savithra Eratne authored at least 9 papers between 2008 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2015

A Thermal-Aware Scheduling Algorithm for Core Migration in Multicore Processors.

Savithra Eratne, Pradeep S. Nair, Eugene John

J. Low Power Electron., 2015

2012

Probability-Based Optimal Sizing of Power-Gating Transistors in Full Adders for Reduced Leakage and High Performance.

Pradeep S. Nair, Savithra Eratne, Eugene B. John

J. Low Power Electron., 2012

Reducing thermal hotspots in microprocessors with expanded component sizing.

Savithra Eratne, Eugene John, Byeong Kil Lee

Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

2010

Leakage and Access Time Tradeoffs for Cache in High Performance Microprocessors.

Savithra Eratne, Claudia Romo, Eugene John, Byeong Kil Lee

Proceedings of the 2010 International Conference on Computer Design, 2010

Leakage Power Analysis of Multi-bit Adders Using Transistor Gate Length Increase.

Savithra Eratne, Claudia Romo, Eugene John

Proceedings of the 2010 International Conference on Computer Design, 2010

2008

Energy Efficiency of Data Compression with Wavelets.

Savithra Eratne, Sebastian Puthenpurayil, Eugene John

Proceedings of the 2008 International Conference on Image Processing, 2008

Effects of Register File Organization on Leakage Power Consumption.

Pradeep S. Nair, Savithra Eratne, Eugene John

Proceedings of the 2008 International Conference on Computer Design, 2008

Topology-related effects of Gated-Vdd and Gated-Vss techniques on full-adder leakage and delay at 65nm and 45 nm.

Pradeep S. Nair, Savithra Eratne, Eugene John

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

Energy efficient lossless image compression with prediction-based transform.

Savithra Eratne, Sebastian Puthenpurayil, Eugene John

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008