Byeongseon Choi

According to our database, Byeongseon Choi authored at least 2 papers in 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

An SRAM-based Error-Free Time Domain Pulse Train Computing-In-Memory Macro achieving 226.14 TOPS/W and 5.782 TOPS/mm².

Edward Jongyoon Choi, Jiho Chun, Byeongseon Choi, Sohmyung Ha, Ik-Joon Chang, Minkyu Je

Proceedings of the 21st International SoC Design Conference, 2024

A 639.38GOPS Hybrid-Domain Logic-Compatible Multi-Level Embedded Flash Computing-in-Memory Macro with Spike-Edge Computation.

Jiho Chun, Edward Jongyoon Choi, Byeongseon Choi, Donghyeon Yi, Sohmyung Ha, Ik-Joon Chang, Minkyu Je

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024