Ik Joon Chang
Orcid: 0000-0002-8871-8695
According to our database1,
Ik Joon Chang
authored at least 58 papers
between 2005 and 2023.
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Bibliography
2023
IEEE J. Emerg. Sel. Topics Circuits Syst., December, 2023
Low-Complexity Double-Node-Upset Resilient Latch Design Using Novel Stacked Cross-Coupled Elements.
IEEE Trans. Circuits Syst. II Express Briefs, September, 2023
IEEE Access, 2023
Proceedings of the International Conference on Electronics, Information, and Communication, 2023
A 333TOPS/W Logic-Compatible Multi-Level Embedded Flash Compute-In-Memory Macro with Dual-Slope Computation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
TRIO: a Novel 10T Ternary SRAM Cell for Area-Efficient In-memory Computing of Ternary Neural Networks.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
2022
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
An SRAM-Based Hybrid Computation-in-Memory Macro Using Current-Reused Differential CCO.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
A 133.6TOPS/W Compute-In-Memory SRAM Macro with Fully Parallel One-Step Multi-Bit Computation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
2021
OBET: On-the-Fly Byte-Level Error Tracking for Correcting and Detecting Faults in Unreliable DRAM Systems.
Sensors, 2021
PR-CIM: a Variation-Aware Binary-Neural-Network Framework for Process-Resilient Computation-in-memory.
CoRR, 2021
IEEE Access, 2021
STT-MRAM Architecture with Parallel Accumulator for In-Memory Binary Neural Networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
2020
A Radiation-Hardened SAR ADC with Delay-Based Dual Feedback Flip-Flops for Sensor Readout Systems.
Sensors, 2020
Comparing Variation-tolerance and SEU/TID-Resilience of Three SRAM Cells in 28nm FD-SOI Technology: 6T, Quatro, and we-Quatro.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020
DRAMA: An Approximate DRAM Architecture for High-performance and Energy-efficient Deep Training System.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
PCM: Precision-Controlled Memory System for Energy Efficient Deep Neural Network Training.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
IEEE Trans. Computers, 2019
Energy-efficient DNN-training with Stretchable DRAM Refresh Controller and Critical-bit Protection.
Proceedings of the 2019 International SoC Design Conference, 2019
St-DRC: Stretchable DRAM Refresh Controller with No Parity-overhead Error Correction Scheme for Energy-efficient DNNs.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
Proceedings of the International SoC Design Conference, 2018
An Approximate Memory Architecture for a Reduction of Refresh Power Consumption in Deep Learning Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
A 28mn FD-SOI 4KB Radiation-hardened 12T SRAM Macro with 0.6 ~ 1V Wide Dynamic Voltage Scaling for Space Applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
Design of Low-Power Voltage Scalable Arithmetic Units with Perfect Timing Error Cancelation.
Circuits Syst. Signal Process., 2017
2016
IEEE Trans. Consumer Electron., 2016
IEEE J. Solid State Circuits, 2016
Subthreshold 8T SRAM sizing utilizing short-channel V<sub>t</sub> roll-off and inverse narrow-width effect.
IEICE Electron. Express, 2016
An adaptive selection of an SRAM cell size for power reduction in an H.264/AVC encoder.
Proceedings of the IEEE International Conference on Consumer Electronics, 2016
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2015
IEICE Trans. Electron., 2015
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015
2014
CPAC: Energy-Efficient Data Collection through Adaptive Selection of Compression Algorithms for Sensor Networks.
Sensors, 2014
a-SAD: power efficient SAD calculator for real time H.264 video encoder using MSB-approximation technique.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
2013
High Performance and Hardware Efficient Multiview Video Coding Frame Scheduling Algorithms and Architectures.
IEEE Trans. Circuits Syst. Video Technol., 2013
A 2-Kb One-Time Programmable Memory for UHF Passive RFID Tag IC in a Standard 0.18 µm CMOS Process.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
IEICE Trans. Electron., 2013
Low complexity image correction using color and focus matching for stereo video coding.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Low-complexity decision directed method for carrier frequency offset estimation of IEEE 802.11ad.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2012
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
IEICE Electron. Express, 2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Low-complexity frame scheduler using shared frame memory for multi-view video coding.
Proceedings of the International SoC Design Conference, 2012
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
A Priority-Based 6T/8T Hybrid SRAM Architecture for Aggressive Voltage Scaling in Video Applications.
IEEE Trans. Circuits Syst. Video Technol., 2011
2010
Exploring Asynchronous Design Techniques for Process-Tolerant and Energy-Efficient Subthreshold Operation.
IEEE J. Solid State Circuits, 2010
Fast and accurate estimation of SRAM read and hold failure probability using critical point sampling.
IET Circuits Devices Syst., 2010
2009
A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS.
IEEE J. Solid State Circuits, 2009
A voltage-scalable & process variation resilient hybrid SRAM architecture for MPEG-4 video processors.
Proceedings of the 46th Design Automation Conference, 2009
2008
A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
2006
IEEE J. Solid State Circuits, 2006
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006
2005
Fast and accurate estimation of nano-scaled SRAM read failure probability using critical point sampling.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005