Byung-Soo Choi

According to our database1, Byung-Soo Choi authored at least 22 papers between 1999 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
Quantum Modular Multiplication.
IEEE Access, 2020

2018
Hierarchical System Mapping for Large-Scale Fault-Tolerant Quantum Computing.
CoRR, 2018

2015
Dual-code quantum computation model.
Quantum Inf. Process., 2015

2014
Efficient quantum algorithms to construct arbitrary Dicke states.
Quantum Inf. Process., 2014

2013
On the construction of stabilizer codes with an arbitrary binary matrix.
Quantum Inf. Process., 2013

Cost comparison between code teleportation and stabilizer sequence methods for quantum code conversion.
Proceedings of the International Conference on Information and Communication Technology Convergence, 2013

Performance simulator based on hardware resources constraints for ion trap quantum computer.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

2012
Optimality proofs of quantum weight decision algorithms.
Quantum Inf. Process., 2012

A Θ( √ n)-depth quantum adder on the 2D NTC quantum computer architecture.
ACM J. Emerg. Technol. Comput. Syst., 2012

Efficient quantum algorithm to construct arbitrary Dicke states
CoRR, 2012

2011
Quantum algorithm for the asymmetric weight decision problem and its generalization to multiple weights.
Quantum Inf. Process., 2011

On the Effect of Quantum Interaction Distance on Quantum Addition Circuits.
ACM J. Emerg. Technol. Comput. Syst., 2011

2010
An $\Theta(\sqrt{n})$-depth Quantum Adder on a 2D NTC Quantum Computer Architecture
CoRR, 2010

2008
Partial resolution for redundant operation table.
Microprocess. Microsystems, 2008

2007
Sure Success Partial Search.
Quantum Inf. Process., 2007

Quantum Partial Search of a Database with Several Target Items.
Quantum Inf. Process., 2007

2005
Cost effective mixed-type value predictor using distributed classification method.
Microprocess. Microsystems, 2005

2004
High Performance Microprocessor Design Methods Exploiting Information Locality and Data Redundancy for Lower Area Cost and Power Consumption.
Proceedings of the Advances in Computer Systems Architecture, 9th Asia-Pacific Conference, 2004

2003
Frequent Value Cache for Low-Power Asynchronous Dual-Rail Bus.
Proceedings of the Integrated Circuit and System Design, 2003

High performance asynchronous bus for SoC.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2001
Asynchronous Array Multiplier with an Asymmetric Parallel Array Structure.
Proceedings of the 19th Conference on Advanced Research in VLSI (ARVLSI 2001), 2001

1999
The Design of Delay Insensitive Asynchronous 16-bit Microprocessor.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999


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