Eun-Gu Jung

According to our database1, Eun-Gu Jung authored at least 19 papers between 2003 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 




Synchronous Real-Time Sampling Technique for Side-Channel Analysis Against Randomly Varying Clock-Based Countermeasures.
IEEE Access, 2021

Stenosis map for volume visualization of constricted tubular structures: Application to coronary artery stenosis.
Comput. Methods Programs Biomed., 2016

Cryptanalysis of INCrypt32 in HID's iCLASS Systems.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Low area and high speed SHA-1 implementation.
Proceedings of the International SoC Design Conference, 2011

A Performance/Energy Analysis and Optimization of Multi-Core Architectures with Voltage Scaling Techniques.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Design and Management of Voltage-Frequency Island Partitioned Networks-on-Chip.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Exploration of Power-Delay Trade-Offs with Heterogeneous Adders by Integer Linear Programming.
J. Circuits Syst. Comput., 2009

Parallel Parity Checksum and Syndrome Generation for Digital Video and Audio Transmission over Cable Channel.
IEICE Trans. Inf. Syst., 2009

An Asymptotic Performance/Energy Analysis and Optimization of Multi-core Architectures.
Proceedings of the Distributed Computing and Networking, 10th International Conference, 2009

Embedding High-Performance Synchronous Routers to Asynchronous Network on Chip.
Proceedings of the 2008 International Conference on Computer Design, 2008

Asynchronous Layered Interface of Multimedia SoCs for Multiple Outstanding Transactions.
J. VLSI Signal Process., 2007

Asynchronous Multiple-Issue On-Chip Bus with In-Order/Out-of-Order Completion.
IEICE Trans. Electron., 2005

Differential Value Encoding for Delay Insensitive Handshake Protocol.
IEICE Trans. Inf. Syst., 2005

Asynchronous Reorder Buffer for Asynchronous On-Chip Bus.
IEICE Trans. Electron., 2005

High Speed JPEG Coder Based on Modularized and Pipelined Architecture with Distributed Control.
Proceedings of the Advances in Multimedia Information Processing, 2005

Design of an Asynchronous Switch Based on Butterfly Fat-Tree for Network-on-Chip Applications.
Proceedings of the Advances in Multimedia Information Processing, 2005

Self-timed Interconnect with Layered Interface Based on Distributed and Modularized Control for Multimedia SoCs.
Proceedings of the Advances in Multimedia Information Processing, 2005

High performance asynchronous on-chip bus with multiple issue and out-of-order/in-order completion.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

High performance asynchronous bus for SoC.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003