C. V. Krishna

According to our database1, C. V. Krishna authored at least 9 papers between 2001 and 2004.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Links

On csauthors.net:

Bibliography

2004
Weighted pseudorandom hybrid BIST.
IEEE Trans. Very Large Scale Integr. Syst., 2004

Achieving high encoding efficiency with partial dynamic LFSR reseeding.
ACM Trans. Design Autom. Electr. Syst., 2004

3-Stage Variable Length Continuous-Flow Scan Vector Decompression Scheme.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

2003
Adjustable Width Linear Combinational Scan Vector Decompression.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Hybrid BIST Using an Incrementally Guided LFSR.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

2002
Reducing Test Dat Volume Using LFSR Reseeding with Seed Compression.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

A methodology for automated insertion of concurrent error detection hardware in synthesizable Verilog RTL.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
Hybrid BIST Based on Weighted Pseudo-Random Testing: A New Test Resource Partitioning Scheme.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Test vector encoding using partial LFSR reseeding.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001


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