Kartik Mohanram

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

2018

MFNW: An MLC/TLC Flip-N-Write Architecture.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2018

ARSENAL: Architecture for Secure Non-Volatile Memories.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2018

LEO: Low Overhead Encryption ORAM for Non-Volatile Memories.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2018

ReadPRO: Read Prioritization Scheduling in ORAM for Efficient Obfuscation in Main Memories.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE International Conference on Computer Design, 2018

RAPID: read acceleration for improved performance and endurance in MLC/TLC NVMs.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2018

ADAM: Architecture for write disturbance mitigation in scaled phase change memory.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

STASH: security architecture for smart hybrid memories.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

ACME: advanced counter mode encryption for secure non-volatile memories.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

CASTLE: compression architecture for secure low latency, low energy, high endurance NVMs.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

2017

ECS: Error-Correcting Strings for Lifetime Improvements in Nonvolatile Memories.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2017

CompEx++: Compression-Expansion Coding for Energy, Latency, and Lifetime Improvements in MLC/TLC NVMs.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2017

Reliable Nonvolatile Memories: Techniques and Measures.

[BibT_eX]

[DOI]

IEEE Des. Test, 2017

Virtual Two-Port Memory Architecture for Asymmetric Memory Technologies.

[BibT_eX]

[DOI]

Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

L3EP: Low latency, low energy program-and-verify for triple-level cell phase change memory.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017

COVERT: Counter OVErflow ReducTion for efficient encryption of non-volatlle memories.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

ASSURE: Authentication Scheme for SecURE Energy Efficient Non-Volatile Memories.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

2016

WOM-Code Solutions for Low Latency and High Endurance in Phase Change Memory.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

Monolayer Transistor SRAMs: Toward Low-Power, Denser Memory Systems.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2016

E3R: Energy Efficient Error Recovery for Multi/Triple-Level Cell Non-volatile Memories.

[BibT_eX]

[DOI]

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

CompEx: Compression-expansion coding for energy, latency, and lifetime improvements in MLC/TLC NVM.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

An Offline Frequent Value Encoding for Energy-Efficient MLC/TLC Non-volatile Memories.

[BibT_eX]

[DOI]

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

SECRET: smartly EnCRypted energy efficient non-volatile memories.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

2015

Two-Port PCM Architecture for Network Processing.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

MFNW: A Flip-N-Write architecture for multi-level cell non-volatile memories.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

Flip-Mirror-Rotate: An Architecture for Bit-write Reduction and Wear Leveling in Non-volatile Memories.

[BibT_eX]

[DOI]

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Monolayer transition metal dichalcogenide and black phosphorus transistors for low power robust SRAM design.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

2014

Time-Borrowing Circuit Designs and Hardware Prototyping for Timing Error Resilience.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2014

Compression architecture for bit-write reduction in non-volatile memory technologies.

[BibT_eX]

[DOI]

David B. Dgien

Nathan Altay Hunter

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014

Write-once-memory-code phase change memory.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

Low Cost Concurrent Error Masking Using Approximate Logic Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Multi-port FinFET SRAM design.

[BibT_eX]

[DOI]

Yirong Zhao

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Mempack: an order of magnitude reduction in the cost, risk, and time for memory compiler certification.

[BibT_eX]

[DOI]

Matthew Wartell

Sundar Iyer

Proceedings of the Design, Automation and Test in Europe, 2013

2012

Ambipolar circuits for analog, mixed-signal, and radio-frequency applications.

[BibT_eX]

[DOI]

Alexander A. Balandin

Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

High performance reliable variable latency carry select addition.

[BibT_eX]

[DOI]

Kai Du

Peter J. Varman

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

Dual-Vth Independent-Gate FinFETs for Low Power Logic Circuits.

[BibT_eX]

[DOI]

Masoud Rostami

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

An Efficient Gate Library for Ambipolar CNTFET Logic.

[BibT_eX]

[DOI]

M. Haykel Ben Jamaa

Giovanni De Micheli

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Static window addition: A new paradigm for the design of variable latency adders.

[BibT_eX]

[DOI]

Kai Du

Peter J. Varman

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Unequal-error-protection codes in SRAMs for mobile multimedia applications.

[BibT_eX]

[DOI]

Xuebei Yang

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Reliability-driven don't care assignment for logic synthesis.

[BibT_eX]

[DOI]

Andrew Zukoski

Proceedings of the Design, Automation and Test in Europe, 2011

Robust 6T Si tunneling transistor SRAM design.

[BibT_eX]

[DOI]

Xuebei Yang

Proceedings of the Design, Automation and Test in Europe, 2011

Universal logic modules based on double-gate carbon nanotube transistors.

[BibT_eX]

[DOI]

Andrew Zukoski

Xuebei Yang

Proceedings of the 48th Design Automation Conference, 2011

2010

Bi-decomposition of large Boolean functions using blocking edge graphs.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Semi-analytical model for schottky-barrier carbon nanotube and graphene nanoribbon transistors.

[BibT_eX]

[DOI]

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Graphene tunneling FET and its applications in low-power circuit design.

[BibT_eX]

[DOI]

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Dominant critical gate identification for power and yield optimization in logic circuits.

[BibT_eX]

[DOI]

Masoud Rostami

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Power consumption of logic circuits in ambipolar carbon nanotube technology.

[BibT_eX]

[DOI]

M. Haykel Ben Jamaa

Giovanni De Micheli

Proceedings of the Design, Automation and Test in Europe, 2010

TIMBER: Time borrowing and error relaying for online timing error resilience.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

Analytical model for TDDB-based performance degradation in combinational logic.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

Novel dual-Vth independent-gate FinFET circuits.

[BibT_eX]

[DOI]

Masoud Rostami

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

Reliability Analysis of Logic Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Soft Error Rate Reduction Using Circuit Optimization and Transient Filter Insertion.

[BibT_eX]

[DOI]

J. Electron. Test., 2009

Modeling stochasticity and robustness in gene regulatory networks.

[BibT_eX]

[DOI]

Bioinform., 2009

Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis.

[BibT_eX]

[DOI]

M. Haykel Ben Jamaa

Giovanni De Micheli

Proceedings of the Design, Automation and Test in Europe, 2009

Masking timing errors on speed-paths in logic circuits.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

Timing-driven optimization using lookahead logic circuits.

[BibT_eX]

[DOI]

Proceedings of the 46th Design Automation Conference, 2009

2008

Graphene nanoribbon FETs: technology exploration and CAD.

[BibT_eX]

[DOI]

Jing Guo

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Tunable Transient Filters for Soft Error Rate Reduction in Combinational Circuits.

[BibT_eX]

[DOI]

Proceedings of the 13th European Test Symposium, 2008

Error Detection and Tolerance for Scaled Electronic Technologies.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

Approximate logic circuits for low overhead, non-intrusive concurrent error detection.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

Technology exploration for graphene nanoribbon FETs.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

2007

Parameter-Variation-Aware Analysis for Noise Robustness.

[BibT_eX]

[DOI]

Mosin Mondal

Yehia Massoud

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Power signal processing: a new perspective for power analysis and optimization.

[BibT_eX]

[DOI]

Lin Zhong

Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Parallel domain decomposition for simulation of large-scale power grids.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Interactive presentation: Single-ended coding techniques for off-chip interconnects to commodity memory.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Accurate and scalable reliability analysis of logic circuits.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

Gate sizing to radiation harden combinational logic.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Design Optimization for Robustness to Single Event Upsets.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Large power grid analysis using domain decomposition.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Elmore model for energy estimation in RC trees.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

Dependable != unaffordable.

[BibT_eX]

[DOI]

Alan L. Cox

Scott Rixner

Proceedings of the 1st Workshop on Architectural and System Support for Improving Software Dependability, 2006

2005

Closed-Form Simulation and Robustness Models for SEU-Tolerant Design.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Simulation of transients caused by single-event upsets in combinational logic.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Structure preserving reduction of frequency-dependent interconnect.

[BibT_eX]

[DOI]

Athanasios C. Antoulas

Proceedings of the 42nd Design Automation Conference, 2005

2004

Lowering power consumption in concurrent checkers via input ordering.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2004

Context-Independent Codes for Off-Chip Interconnects.

[BibT_eX]

[DOI]

Scott Rixner

Proceedings of the Power-Aware Computer Systems, 4th International Workshop, 2004

Analysis of delay caused by bridging faults in RLC interconnects.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Cost-effective radiation hardening technique for combinational logic.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

2003

Eliminating Non-Determinism During Test of High-Speed Source Synchronous Differential Buses.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Synthesis of Low-Cost Parity-Based Partially Self-Checking Circuits.

[BibT_eX]

[DOI]

Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

2002

A methodology for automated insertion of concurrent error detection hardware in synthesizable Verilog RTL.

[BibT_eX]

[DOI]

C. V. Krishna

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Input Ordering in Concurrent Checkers to Reduce Power Consumption.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

1999

An Embedded Core DFT Scheme to Obtain Highly Compressed Test Sets.

[BibT_eX]

[DOI]

Abhijit Jas