Carlos Molina

Orcid: 0000-0003-1955-0128

Affiliations:
  • Universitat Rovira i Virgili, Tarragona, Spain


According to our database1, Carlos Molina authored at least 31 papers between 1999 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2020
Predicting Topology Propagation Messages in Mobile Ad Hoc Networks: The Value of History.
Sensors, 2020

A Low-Cost Multicomputer for Teaching Environments.
Rev. Iberoam. de Tecnol. del Aprendiz., 2020

2017
Real-Time Communication Support for Underwater Acoustic Sensor Networks.
Sensors, 2017

Towards Decentralised Resilient Community Cloud Infrastructures.
CoRR, 2017

Towards decentralised resilient community clouds.
Proceedings of the 2nd Workshop on Middleware for Edge Clouds & Cloudlets, 2017

2016
Scheduling Real-Time Traffic in Underwater Acoustic Wireless Sensor Networks.
Proceedings of the Ubiquitous Computing and Ambient Intelligence, 2016

2015
Time series analysis to predict link quality of wireless community networks.
Comput. Networks, 2015

Tracking and Predicting End-to-End Quality in Wireless Community Networks.
Proceedings of the 3rd International Conference on Future Internet of Things and Cloud, 2015

2014
Network aware performance evaluation of prefetching techniques in CMPs.
Simul. Model. Pract. Theory, 2014

Energy-Aware Topology Control Strategy for Human-Centric Wireless Sensor Networks.
Sensors, 2014

Tracking and predicting link quality in wireless community networks.
Proceedings of the IEEE 10th International Conference on Wireless and Mobile Computing, 2014

Using a History-Based Approach to Predict Topology Control Information in Mobile Ad Hoc Networks.
Proceedings of the Internet and Distributed Computing Systems, 2014

2013
Replacement techniques for dynamic NUCA cache designs on CMPs.
J. Supercomput., 2013

2012
The migration prefetcher: Anticipating data promotion in dynamic NUCA caches.
ACM Trans. Archit. Code Optim., 2012

Reducing energy consumption in human-centric wireless sensor networks.
Proceedings of the IEEE International Conference on Systems, Man, and Cybernetics, 2012

2011
Case for a field-programmable gate array multicore hybrid machine for an image-processing application.
J. Electronic Imaging, 2011

HK-NUCA: Boosting Data Searches in Dynamic Non-Uniform Cache Architectures for Chip Multiprocessors.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

Implementing a hybrid SRAM / eDRAM NUCA architecture.
Proceedings of the 18th International Conference on High Performance Computing, 2011

Beforehand Migration on D-NUCA Caches.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2010
OLSRp: Predicting Control Information to Achieve Scalability in OLSR Ad Hoc Networks.
Proceedings of the Mobile Networks and Management - Second International ICST Conference, 2010

The auction: optimizing banks usage in Non-Uniform Cache Architectures.
Proceedings of the 24th International Conference on Supercomputing, 2010

2009
LRU-PEA: A smart replacement policy for non-uniform cache architectures on chip multiprocessors.
Proceedings of the 27th International Conference on Computer Design, 2009

Last Bank: Dealing with Address Reuse in Non-Uniform Cache Architecture for CMPs.
Proceedings of the Euro-Par 2009 Parallel Processing, 2009

2005
Reducing Misspeculation Penalty in Trace-Level Speculative Multithreaded Architectures.
Proceedings of the High-Performance Computing - 6th International Symposium, 2005

Compiler analysis for trace-level speculative multithreaded architectures.
Proceedings of the 9th Annual Workshop on Interaction between Compilers and Computer Architectures, 2005

2003
Non redundant data cache.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Value Compression to Reduce Power in Data Caches.
Proceedings of the Euro-Par 2003. Parallel Processing, 2003

2002
Trace-Level Speculative Multithreaded Architecture.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

1999
Dynamic removal of redundant computations.
Proceedings of the 13th international conference on Supercomputing, 1999

Trace-Level Reuse.
Proceedings of the International Conference on Parallel Processing 1999, 1999

Reducing Memory Traffic Via Redundant Store Instructions.
Proceedings of the High-Performance Computing and Networking, 7th International Conference, 1999


  Loading...