Antonio González
Orcid: 0000-0002-0009-0996Affiliations:
- Polytechnic University of Catalonia (UPC), Department of Computer Architecture
- Intel Labs, Intel Barcelona Research Center
According to our database1,
Antonio González
authored at least 324 papers
between 1988 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
2023
J. Parallel Distributed Comput., April, 2023
ACM Trans. Embed. Comput. Syst., March, 2023
Irregular accesses reorder unit: improving GPGPU memory coalescing for graph-based workloads.
J. Supercomput., 2023
ReuseSense: With Great Reuse Comes Greater Efficiency; Effectively Employing Computation Reuse on General-Purpose CPUs.
CoRR, 2023
An Energy-Efficient Near-Data Processing Accelerator for DNNs that Optimizes Data Accesses.
CoRR, 2023
ReDy: A Novel ReRAM-centric Dynamic Quantization Approach for Energy-efficient CNN Inference.
CoRR, 2023
δLTA: Decoupling Camera Sampling from Processing to Avoid Redundant Computations in the Vision Pipeline.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023
Proceedings of the 30th IEEE International Conference on High Performance Computing, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the 32nd International Conference on Parallel Architectures and Compilation Techniques, 2023
QeiHaN: An Energy-Efficient DNN Accelerator that Leverages Log Quantization in NDP Architectures.
Proceedings of the 32nd International Conference on Parallel Architectures and Compilation Techniques, 2023
Proceedings of the 32nd International Conference on Parallel Architectures and Compilation Techniques, 2023
2022
Omega-Test: A Predictive Early-Z Culling to Improve the Graphics Pipeline Energy-Efficiency.
IEEE Trans. Vis. Comput. Graph., 2022
Dynamic sampling rate: harnessing frame coherence in graphics applications for energy-efficient GPUs.
J. Supercomput., 2022
Energy-Efficient Stream Compaction Through Filtering and Coalescing Accesses in GPGPU Memory Partitions.
IEEE Trans. Computers, 2022
ACM Trans. Archit. Code Optim., 2022
ACM Trans. Archit. Code Optim., 2022
Mach. Learn. Knowl. Extr., 2022
CREW: Computation reuse and efficient weight storage for hardware-accelerated MLPs and RNNs.
J. Syst. Archit., 2022
J. Syst. Archit., 2022
CoRR, 2022
Proceedings of the 30th Euromicro International Conference on Parallel, 2022
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022
Proceedings of the International IEEE Symposium on Performance Analysis of Systems and Software, 2022
Proceedings of the International IEEE Symposium on Performance Analysis of Systems and Software, 2022
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022
2021
Fast and Accurate SER Estimation for Large Combinational Blocks in Early Stages of the Design.
IEEE Trans. Sustain. Comput., 2021
CoRR, 2021
Proceedings of the 33rd IEEE International Symposium on Computer Architecture and High Performance Computing, 2021
2020
IEEE Trans. Computers, 2020
ACM Trans. Archit. Code Optim., 2020
Proceedings of the IEEE International Symposium on Workload Characterization, 2020
Proceedings of the 27th IEEE International Conference on High Performance Computing, 2020
2019
Visibility Rendering Order: Improving Energy Efficiency on Mobile GPUs through Frame Coherence.
IEEE Trans. Parallel Distributed Syst., 2019
IEEE Trans. Computers, 2019
SyRA: Early System Reliability Analysis for Cross-Layer Soft Errors Resilience in Memory Arrays of Microprocessor Systems.
IEEE Trans. Computers, 2019
IEEE Micro, 2019
LSTM-Sharp: An Adaptable, Energy-Efficient Hardware Accelerator for Long Short-Term Memory.
CoRR, 2019
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019
Proceedings of the 46th International Symposium on Computer Architecture, 2019
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019
Early Visibility Resolution for Removing Ineffectual Computations in the Graphics Pipeline.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019
Proceedings of the 28th International Conference on Parallel Architectures and Compilation Techniques, 2019
2018
IEEE Trans. Multi Scale Comput. Syst., 2018
IEEE Micro, 2018
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018
Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques, 2018
2017
Low-Power Automatic Speech Recognition Through a Mobile GPU and a Viterbi Accelerator.
IEEE Micro, 2017
J. Parallel Distributed Comput., 2017
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017
MeRLiN: Exploiting Dynamic Instruction Behavior for Fast and Accurate Microarchitecture Level Reliability Assessment.
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017
Proceedings of the 2017 International Symposium on Code Generation and Optimization, 2017
Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017
2016
IEEE Trans. Parallel Distributed Syst., 2016
Assisting Static Compiler Vectorization with a Speculative Dynamic Vectorizer in an HW/SW Codesigned Environment.
ACM Trans. Comput. Syst., 2016
IEEE Trans. Computers, 2016
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016
Proceedings of the 2016 IEEE International Test Conference, 2016
Quantitative characterization of the software layer of a HW/SW co-designed processor.
Proceedings of the 2016 IEEE International Symposium on Workload Characterization, 2016
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
Proceedings of the 23rd IEEE International Conference on High Performance Computing, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
Proceedings of the 27th International Symposium on Computer Architecture and High Performance Computing, 2015
Proceedings of the 48th International Symposium on Microarchitecture, 2015
Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015
2014
Efficient Power Gating of SIMD Accelerators Through Dynamic Selective Devectorization in an HW/SW Codesigned Environment.
ACM Trans. Archit. Code Optim., 2014
Avoiding core's DUE & SDC via acoustic wave detectors and tailored error containment and recovery.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014
Proceedings of the ACM International Conference on Supercomputing 25th Anniversary Volume, 2014
iRMW: A low-cost technique to reduce NBTI-dependent parametric failures in L1 data caches.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the 12th Annual IEEE/ACM International Symposium on Code Generation and Optimization, 2014
Proceedings of the Computing Frontiers Conference, CF'14, 2014
2013
Dynamic Selective Devectorization for Efficient Power Gating of SIMD Units in a HW/SW Co-Designed Environment.
Proceedings of the 25th International Symposium on Computer Architecture and High Performance Computing, 2013
Proceedings of the International Symposium on Quality Electronic Design, 2013
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
Proceedings of the 10th IEEE International Conference on High Performance Computing and Communications & 2013 IEEE International Conference on Embedded and Ubiquitous Computing, 2013
Speculative dynamic vectorization to assist static vectorization in a HW/SW co-designed environment.
Proceedings of the 20th Annual International Conference on High Performance Computing, 2013
Performance analysis and predictability of the software layer in dynamic binary translators/optimizers.
Proceedings of the Computing Frontiers Conference, 2013
2012
ACM Trans. Archit. Code Optim., 2012
Integr., 2012
DDGacc: boosting dynamic DDG-based binary optimizations through specialized hardware support.
Proceedings of the 8th International Conference on Virtual Execution Environments, 2012
Proceedings of the Security and Privacy in Communication Networks, 2012
Improving the Performance Efficiency of an IDS by Exploiting Temporal Locality in Network Traffic.
Proceedings of the 20th IEEE International Symposium on Modeling, 2012
Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2012
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012
Hardware/Software Mechanisms for Protecting an IDS against Algorithmic Complexity Attacks.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012
2011
Trans. High Perform. Embed. Archit. Compil., 2011
Trans. High Perform. Embed. Archit. Compil., 2011
IEEE Trans. Computers, 2011
TRAMS Project: Variability and Reliability of SRAM Memories in sub-22 nm Bulk-CMOS Technologies.
Proceedings of the 2nd European Future Technologies Conference and Exhibition, 2011
Design of complex circuits using the Via-Configurable transistor array regular layout fabric.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011
Proceedings of the 23rd International Symposium on Computer Architecture and High Performance Computing, 2011
Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011
Global productiveness propagation: a code optimization technique to speculatively prune useless narrow computations.
Proceedings of the ACM SIGPLAN/SIGBED 2011 conference on Languages, 2011
Thread shuffling: combining DVFS and thread migration toreduce energy consumptions for multi-core systems.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011
HK-NUCA: Boosting Data Searches in Dynamic Non-Uniform Cache Architectures for Chip Multiprocessors.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011
Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitors.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011
Hardware/software-based diagnosis of load-store queues using expandable activity logs.
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011
Proceedings of the High Performance Embedded Architectures and Compilers, 2011
Proceedings of the 18th International Conference on High Performance Computing, 2011
Proceedings of the 8th Conference on Computing Frontiers, 2011
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011
A Co-designed HW/SW Approach to General Purpose Program Acceleration Using a Programmable Functional Unit.
Proceedings of the 15th Workshop on Interaction between Compilers and Computer Architectures, 2011
2010
Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, ISBN: 978-3-031-01729-2, 2010
IEEE Trans. Computers, 2010
Thread-management techniques to maximize efficiency in multicore and simultaneous multithreaded microprocessors.
ACM Trans. Archit. Code Optim., 2010
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010
Proceedings of the 2011 IEEE International Test Conference, 2010
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
Proceedings of the 24th International Conference on Supercomputing, 2010
Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010
Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability.
Proceedings of the Design, Automation and Test in Europe, 2010
2009
ACM Trans. Comput. Syst., 2009
IEEE Trans. Dependable Secur. Comput., 2009
AGAMOS: A Graph-Based Approach to Modulo Scheduling for Clustered Microarchitectures.
IEEE Trans. Computers, 2009
ACM Trans. Archit. Code Optim., 2009
ACM Trans. Archit. Code Optim., 2009
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009
Boosting single-thread performance in multi-core systems through fine-grain multi-threading.
Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009
Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009
Using Coherence Information and Decay Techniques to Optimize L2 Cache Leakage in CMPs.
Proceedings of the ICPP 2009, 2009
LRU-PEA: A smart replacement policy for non-uniform cache architectures on chip multiprocessors.
Proceedings of the 27th International Conference on Computer Design, 2009
Proceedings of the 16th International Conference on High Performance Computing, 2009
Proceedings of the Euro-Par 2009 Parallel Processing, 2009
Proceedings of the Architecture of Computing Systems, 2009
Proceedings of the PACT 2009, 2009
Proceedings of the PACT 2009, 2009
2008
IEEE Trans. Parallel Distributed Syst., 2008
IEEE Trans. Parallel Distributed Syst., 2008
Proceedings of the 9th workshop on MEmory performance, 2008
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008
Meeting points: using thread criticality to adapt multicore hardware to parallel regions.
Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, 2008
2007
IEEE Trans. Parallel Distributed Syst., 2007
Guest Editors' Introduction: Micro's Top Picks from the Microarchitecture Conferences.
IEEE Micro, 2007
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 2007
Proceedings of the 2007 workshop on MEmory performance, 2007
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
Proceedings of the 13st International Conference on High-Performance Computer Architecture (HPCA-13 2007), 2007
Proceedings of the Fifth International Symposium on Code Generation and Optimization (CGO 2007), 2007
Proceedings of the Fifth International Symposium on Code Generation and Optimization (CGO 2007), 2007
Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007
2006
IEEE Trans. Computers, 2006
J. Embed. Comput., 2006
Concurr. Comput. Pract. Exp., 2006
Independent front-end and back-end dynamic voltage scaling for a GALS microarchitecture.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006
Proceedings of the 20th Annual International Conference on Supercomputing, 2006
Design space exploration for multicore architectures: a power/performance/thermal view.
Proceedings of the 20th Annual International Conference on Supercomputing, 2006
Proceedings of the 20th Annual International Conference on Supercomputing, 2006
2005
On-Chip Interconnects and Instruction Steering Schemes for Clustered Microarchitectures.
IEEE Trans. Parallel Distributed Syst., 2005
ACM Trans. Program. Lang. Syst., 2005
IEEE Trans. Computers, 2005
ACM Trans. Archit. Code Optim., 2005
Int. J. High Perform. Comput. Netw., 2005
Mitosis compiler: an infrastructure for speculative threading based on pre-computation slices.
Proceedings of the ACM SIGPLAN 2005 Conference on Programming Language Design and Implementation, 2005
Proceedings of the ACM SIGPLAN 2005 Conference on Programming Language Design and Implementation, 2005
The Mitosis Speculative Multithreaded Architectures.
Proceedings of the Parallel Computing: Current & Future Issues of High-End Computing, 2005
Reducing Misspeculation Penalty in Trace-Level Speculative Multithreaded Architectures.
Proceedings of the High-Performance Computing - 6th International Symposium, 2005
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
Proceedings of the 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 2005
Proceedings of the 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 2005
Proceedings of the Euro-Par 2005, Parallel Processing, 11th International Euro-Par Conference, Lisbon, Portugal, August 30, 2005
Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques (PACT 2005), 2005
Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques (PACT 2005), 2005
Proceedings of the 9th Annual Workshop on Interaction between Compilers and Computer Architectures, 2005
2004
ACM Trans. Program. Lang. Syst., 2004
Thread Partitioning and Value Prediction for Exploiting Speculative Thread-Level Parallelism.
IEEE Trans. Computers, 2004
Removing communications in clustered microarchitectures through instruction replication.
ACM Trans. Archit. Code Optim., 2004
Proceedings of the 3rd Workshop on Memory Performance Issues, 2004
Proceedings of the 18th Annual International Conference on Supercomputing, 2004
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004
Proceedings of the 10th International Conference on High-Performance Computer Architecture (HPCA-10 2004), 2004
Proceedings of the 2nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2004), 2004
2003
Proceedings of the International Conference on Measurements and Modeling of Computer Systems, 2003
Proceedings of the 36th Annual International Symposium on Microarchitecture, 2003
Proceedings of the 36th Annual International Symposium on Microarchitecture, 2003
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003
Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), 2003
Proceedings of the High Performance Computing - HiPC 2003, 10th International Conference, 2003
Proceedings of the Euro-Par 2003. Parallel Processing, 2003
Local Scheduling Techniques for Memory Coherence in a Clustered VLIW Processor with a Distributed Data Cache.
Proceedings of the 1st IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2003), 2003
Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques (PACT 2003), 27 September, 2003
2002
IEEE Trans. Parallel Distributed Syst., 2002
SIGARCH Comput. Archit. News, 2002
Effective instruction scheduling techniques for an interleaved cache clustered VLIW processor.
Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002
Proceedings of the Languages and Compilers for Parallel Computing, 15th Workshop, 2002
Proceedings of the 29th International Symposium on Computer Architecture (ISCA 2002), 2002
Proceedings of the 16th international conference on Supercomputing, 2002
Proceedings of the 16th international conference on Supercomputing, 2002
Proceedings of the 16th international conference on Supercomputing, 2002
Proceedings of the 31st International Conference on Parallel Processing Workshops (ICPP 2002 Workshops), 2002
Proceedings of the 31st International Conference on Parallel Processing (ICPP 2002), 2002
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002
Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), 2002
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 2002
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 2002
2001
IEEE Trans. Computers, 2001
IEEE Trans. Computers, 2001
Parallel Comput., 2001
J. Instr. Level Parallelism, 2001
Int. J. Parallel Program., 2001
CALMANT: A Systematic Method for the Execution of Hypercube Algorithms in Multiprocessor Systems.
Computación y Sistemas, 2001
CALMANT: Un Método Sistemático para la Ejecución de Algoritmos Hipercubo en Sistemas Multiprocesador.
Computación y Sistemas, 2001
Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001
Proceedings of the 28th Annual International Symposium on Computer Architecture, 2001
Proceedings of the 15th international conference on Supercomputing, 2001
Selective Branch Prediction Reversal By Correlating with Data Values and Control Flow.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001
Proceedings of the High Performance Computing - HiPC 2001, 8th International Conference, 2001
A Unified Modulo Scheduling and Register Allocation Technique for Clustered Processors.
Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques (PACT 2001), 2001
2000
J. Instr. Level Parallelism, 2000
Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, 2000
Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, 2000
Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, 2000
Proceedings of the 13th International Symposium on System Synthesis, 2000
Proceedings of the 2000 IEEE International Symposium on Performance Analysis of Systems and Software, 2000
Proceedings of the 27th International Symposium on Computer Architecture (ISCA 2000), 2000
Proceedings of the 14th International Parallel & Distributed Processing Symposium (IPDPS'00), 2000
Proceedings of the 14th international conference on Supercomputing, 2000
The Effectiveness of Loop Unrolling for Modulo Scheduling in Clustered VLIW Architectures.
Proceedings of the 2000 International Conference on Parallel Processing, 2000
Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, 2000
Proceedings of the Euro-Par 2000, Parallel Processing, 6th International Euro-Par Conference, Munich, Germany, August 29, 2000
Complete Exchange Algorithms for Meshes and Tori Using a Systematic Approach (Research Note).
Proceedings of the Euro-Par 2000, Parallel Processing, 6th International Euro-Par Conference, Munich, Germany, August 29, 2000
1999
Low Communication Overhead Jacobi Algorithms for Eigenvalues Computation on Hypercubes.
J. Supercomput., 1999
J. Parallel Distributed Comput., 1999
Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, 1999
Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, 1999
Proceedings of the 13th international conference on Supercomputing, 1999
Proceedings of the 13th international conference on Supercomputing, 1999
Proceedings of the 13th international conference on Supercomputing, 1999
Proceedings of the International Conference on Parallel Processing 1999, 1999
Proceedings of the High-Performance Computing and Networking, 7th International Conference, 1999
Proceedings of the High-Performance Computing and Networking, 7th International Conference, 1999
Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, 1999
Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques, 1999
Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques, 1999
1998
Parallel Comput., 1998
Proceedings of the Vector and Parallel Processing, 1998
A Jacobi-based algorithm for computing symmetric eigenvalues and eigenvectors in a two-dimensional mesh.
Proceedings of the Sixth Euromicro Workshop on Parallel and Distributed Processing, 1998
Proceedings of the 12th International Parallel Processing Symposium / 9th Symposium on Parallel and Distributed Processing (IPPS/SPDP '98), March 30, 1998
Proceedings of the 12th international conference on Supercomputing, 1998
Proceedings of the 12th international conference on Supercomputing, 1998
Proceedings of the Fourth International Symposium on High-Performance Computer Architecture, Las Vegas, Nevada, USA, January 31, 1998
Proceedings of the Fourth International Symposium on High-Performance Computer Architecture, Las Vegas, Nevada, USA, January 31, 1998
Proceedings of the Thirty-First Annual Hawaii International Conference on System Sciences, 1998
Proceedings of the Euro-Par '98 Parallel Processing, 1998
Proceedings of the 24th EUROMICRO '98 Conference, 1998
Proceedings of the 24th EUROMICRO '98 Conference, 1998
Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques, 1998
1997
Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, 1997
Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, 1997
Proceedings of the 11th international conference on Supercomputing, 1997
Proceedings of the 11th international conference on Supercomputing, 1997
Proceedings of the Fourth International on High-Performance Computing, 1997
Proceedings of the Euro-Par '97 Parallel Processing, 1997
Proceedings of the Euro-Par '97 Parallel Processing, 1997
Proceedings of the 1997 International Conference on Application-Specific Systems, 1997
Proceedings of the 1997 Conference on Parallel Architectures and Compilation Techniques (PACT '97), 1997
1996
Proceedings of the Euro-Par '96 Parallel Processing, 1996
Proceedings of the Fifth International Conference on Parallel Architectures and Compilation Techniques, 1996
1995
IEEE Trans. Parallel Distributed Syst., 1995
Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing (PDP '95), 1995
Proceedings of the Applied Parallel Computing, 1995
Proceedings of the 28th Annual International Symposium on Microarchitecture, Ann Arbor, Michigan, USA, November 29, 1995
Proceedings of the 9th international conference on Supercomputing, 1995
1994
Perform. Evaluation, 1994
Proceedings of the Second Euromicro Workshop on Parallel and Distributed Processing, 1994
The Multipath Parallel Execution Model for Prolog.
Proceedings of the First International Symposium on Parallel Symbolic Computation, 1994
Proceedings of the Sixth International Conference on Tools with Artificial Intelligence, 1994
Combining depth-first and breadth-first search in Prolog execution.
Proceedings of the 1994 Joint Conference on Declarative Programming, 1994
1993
Microprocess. Microprogramming, 1993
Proceedings of the International Conference on Application-Specific Array Processors, 1993
1989
Proceedings of the 3rd international conference on Supercomputing, 1989
1988
Microprocess. Microprogramming, 1988