Timothy M. Jones

Affiliations:
  • University of Cambridge, UK


According to our database1, Timothy M. Jones authored at least 73 papers between 2005 and 2023.

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Bibliography

2023
Decoupled Vector Runahead.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

Dynamic Allocation of Processor Cores to Graph Applications on Commodity Servers.
Proceedings of the 32nd International Conference on Parallel Architectures and Compilation Techniques, 2023

2022
Vector Runahead for Indirect Memory Accesses.
IEEE Micro, 2022

MineSweeper: a "clean sweep" for drop-in use-after-free prevention.
Proceedings of the ASPLOS '22: 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Lausanne, Switzerland, 28 February 2022, 2022

2021
Timed hyperproperties.
Inf. Comput., 2021

Compendia: reducing virtual-memory costs via selective densification.
Proceedings of the ISMM '21: 2021 ACM SIGPLAN International Symposium on Memory Management, 2021

Speculative Vectorisation with Selective Replay.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

Vector Runahead.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

Quantifying the Semantic Gap Between Serial and Parallel Programming.
Proceedings of the IEEE International Symposium on Workload Characterization, 2021

ParaDox: Eliminating Voltage Margins via Heterogeneous Fault Tolerance.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

Cinnamon: A Domain-Specific Language for Binary Profiling and Monitoring.
Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization, 2021

2020
Software Prefetching for Unstructured Mesh Applications.
ACM Trans. Parallel Comput., 2020

Duplo: a framework for OCaml post-link optimisation.
Proc. ACM Program. Lang., 2020

The gem5 Simulator: Version 20.0+.
CoRR, 2020


MarkUs: Drop-in use-after-free prevention for low-level languages.
Proceedings of the 2020 IEEE Symposium on Security and Privacy, 2020

Prefetching in functional languages.
Proceedings of the ISMM '20: 2020 ACM SIGPLAN International Symposium on Memory Management, 2020

MuonTrap: Preventing Cross-Domain Spectre-Like Attacks by Capturing Speculative State.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

HALO: post-link heap-layout optimisation.
Proceedings of the CGO '20: 18th ACM/IEEE International Symposium on Code Generation and Optimization, 2020

The Guardian Council: Parallel Programmable Hardware Security.
Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020

2019
The janus triad: exploiting parallelism through dynamic binary modification.
Proceedings of the 15th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments, 2019

On Verifying Timed Hyperproperties.
Proceedings of the 26th International Symposium on Temporal Representation and Reasoning, 2019

CHERIvoke: Characterising Pointer Revocation using CHERI Capabilities for Temporal Memory Safety.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

ParaMedic: Heterogeneous Parallel Error Correction.
Proceedings of the 49th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2019

Janus: Statically-Driven and Profile-Guided Automatic Dynamic Binary Parallelisation.
Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization, 2019

2018
Software Prefetching for Indirect Memory Accesses: A Microarchitectural Perspective.
ACM Trans. Comput. Syst., 2018

Parallel Error Detection Using Heterogeneous Cores.
Proceedings of the 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2018

An Event-Triggered Programmable Prefetcher for Irregular Workloads.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

2017
On Microarchitectural Mechanisms for Cache Wearout Reduction.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Automatically accelerating non-numerical programs by architecture-compiler co-design.
Commun. ACM, 2017

High performance fault tolerance through predictive instruction re-execution.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

Software prefetching for indirect memory accesses.
Proceedings of the 2017 International Symposium on Code Generation and Optimization, 2017

2016
Enhancing the L1 Data Cache Design to Mitigate HCI.
IEEE Comput. Archit. Lett., 2016

Lynx: Using OS and Hardware Support for Fast Fine-Grained Inter-Core Communication.
Proceedings of the 2016 International Conference on Supercomputing, 2016

Graph Prefetching Using Data Structure Knowledge.
Proceedings of the 2016 International Conference on Supercomputing, 2016

Energy Efficient And Low Latency Interconnection Network For Multicast Invalidates In Shared Memory Systems.
Proceedings of the 1st International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, 2016

Performance implications of transient loop-carried data dependences in automatically parallelized loops.
Proceedings of the 25th International Conference on Compiler Construction, 2016

COMET: communication-optimised multi-threaded error-detection technique.
Proceedings of the 2016 International Conference on Compilers, 2016

2015
REPAIR: Hard-error recovery via re-execution.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

Coherence based message prediction for optically interconnected chip multiprocessors.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

PSLP: padded SLP automatic vectorization.
Proceedings of the 13th Annual IEEE/ACM International Symposium on Code Generation and Optimization, 2015

Throttling Automatic Vectorization: When Less is More.
Proceedings of the 2015 International Conference on Parallel Architectures and Compilation, 2015

2014
Towards zero latency photonic switching in shared memory networks.
Concurr. Comput. Pract. Exp., 2014

HELIX-RC: An architecture-compiler co-design for automatic parallelization of irregular programs.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

ALLARM: Optimizing sparse directories for thread-local data.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Dynamic microarchitectural adaptation using machine learning.
ACM Trans. Archit. Code Optim., 2013

The Smart Cache: An Energy-Efficient Cache Architecture Through Dynamic Adaptation.
Int. J. Parallel Program., 2013

Full system simulation of optically interconnected chip multiprocessors using gem5.
Proceedings of the 2013 Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC), 2013

RECAP: Region-Aware Cache Partitioning.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

2012
Exploring and Predicting the Effects of Microarchitectural Parameters and Compiler Optimizations on Performance and Energy.
ACM Trans. Embed. Comput. Syst., 2012

The migration prefetcher: Anticipating data promotion in dynamic NUCA caches.
ACM Trans. Archit. Code Optim., 2012

Helix: Making the Extraction of Thread-Level Parallelism Mainstream.
IEEE Micro, 2012

Cooperative partitioning: Energy-efficient cache partitioning for high-performance CMPs.
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

The HELIX project: overview and directions.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

HELIX: automatic parallelization of irregular programs for chip multiprocessing.
Proceedings of the 10th Annual IEEE/ACM International Symposium on Code Generation and Optimization, 2012

Energy-efficient cache partitioning for future CMPs.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2011
Compiler Directed Issue Queue Energy Reduction.
Trans. High Perform. Embed. Archit. Compil., 2011

An Empirical Architecture-Centric Approach to Microarchitectural Design Space Exploration.
IEEE Trans. Computers, 2011

Smart cache: A self adaptive cache architecture for energy efficiency.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

Link-time optimization for power efficiency in a tagless instruction cache.
Proceedings of the CGO 2011, 2011

A reconfigurable cache architecture for energy efficiency.
Proceedings of the 8th Conference on Computing Frontiers, 2011

Beforehand Migration on D-NUCA Caches.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2010
A Predictive Model for Dynamic Microarchitectural Adaptivity Control.
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

2009
Energy-efficient register caching with compiler assistance.
ACM Trans. Archit. Code Optim., 2009

Exploring the limits of early register release: Exploiting compiler analysis.
ACM Trans. Archit. Code Optim., 2009

Portable compiler optimisation across embedded programs and microarchitectures using machine learning.
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

Rapid early-stage microarchitecture design using predictive models.
Proceedings of the 27th International Conference on Computer Design, 2009

2008
Instruction Cache Energy Saving Through Compiler Way-Placement.
Proceedings of the Design, Automation and Test in Europe, 2008

Exploring and predicting the architecture/optimising compiler co-design space.
Proceedings of the 2008 International Conference on Compilers, 2008

2007
Microarchitectural Design Space Exploration Using an Architecture-Centric Approach.
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 2007

2006
Compiler-directed energy savings in superscalar processors.
PhD thesis, 2006

2005
Software Directed Issue Queue Power Reduction.
Proceedings of the 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 2005

Compiler Directed Early Register Release.
Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques (PACT 2005), 2005


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