Jordi Tubella

CoRR, 2024

Memento: An Adaptive, Compiler-Assisted Register File Cache for GPUs.

[BibT_eX]

[DOI]

José-María Arnau

Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024

2023

A Lightweight, Compiler-Assisted Register File Cache for GPGPU.

[BibT_eX]

[DOI]

José-María Arnau

CoRR, 2023

Lightweight Register File Caching in Collector Units for GPUs.

[BibT_eX]

[DOI]

José-María Arnau

Proceedings of the 15th Workshop on General Purpose Processing Using GPU, 2023

2018

Performance Analysis and Optimization of Automatic Speech Recognition.

[BibT_eX]

[DOI]

IEEE Trans. Multi Scale Comput. Syst., 2018

A Novel Register Renaming Technique for Out-of-Order Processors.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

2017

Shared resource aware scheduling on power-constrained tiled many-core processors.

[BibT_eX]

[DOI]

Sudhanshu Shekhar Jha

J. Parallel Distributed Comput., 2017

An Ultra Low-Power Hardware Accelerator for Acoustic Scoring in Speech Recognition.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017

2015

Chrysso: an integrated power manager for constrained many-core processors.

[BibT_eX]

[DOI]

Sudhanshu Shekhar Jha

Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015

2012

Improving the Resilience of an IDS against Performance Throttling Attacks.

[BibT_eX]

[DOI]

Proceedings of the Security and Privacy in Communication Networks, 2012

Improving the Performance Efficiency of an IDS by Exploiting Temporal Locality in Network Traffic.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Symposium on Modeling, 2012

Exploiting temporal locality in network traffic using commodity multi-cores.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2012

Hardware/Software Mechanisms for Protecting an IDS against Algorithmic Complexity Attacks.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

2011

A Performance and Area Efficient Architecture for Intrusion Detection Systems.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

2005

Reducing Misspeculation Penalty in Trace-Level Speculative Multithreaded Architectures.

[BibT_eX]

[DOI]

Proceedings of the High-Performance Computing - 6th International Symposium, 2005

Compiler analysis for trace-level speculative multithreaded architectures.

[BibT_eX]

[DOI]

Proceedings of the 9th Annual Workshop on Interaction between Compilers and Computer Architectures, 2005

2004

Thread Partitioning and Value Prediction for Exploiting Speculative Thread-Level Parallelism.

[BibT_eX]

[DOI]

Pedro Marcuello

IEEE Trans. Computers, 2004

2003

Non redundant data cache.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Value Compression to Reduce Power in Data Caches.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2003. Parallel Processing, 2003

2002

Trace-Level Speculative Multithreaded Architecture.

[BibT_eX]

[DOI]

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

1999

Value Prediction for Speculative Multithreaded Architectures.

[BibT_eX]

[DOI]

Pedro Marcuello

Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, 1999

Dynamic removal of redundant computations.

[BibT_eX]

[DOI]

Proceedings of the 13th international conference on Supercomputing, 1999

Trace-Level Reuse.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Parallel Processing 1999, 1999

Reducing Memory Traffic Via Redundant Store Instructions.

[BibT_eX]

[DOI]

Proceedings of the High-Performance Computing and Networking, 7th International Conference, 1999

1998

Speculative Multithreaded Processors.

[BibT_eX]

[DOI]

Pedro Marcuello

Proceedings of the 12th international conference on Supercomputing, 1998

Control Speculation in Multithreaded Processors through Dynamic Loop Detection.

[BibT_eX]

[DOI]

Proceedings of the Fourth International Symposium on High-Performance Computer Architecture, Las Vegas, Nevada, USA, January 31, 1998

1996

Multipath: un sistema para la programación lógica.

[BibT_eX]

[DOI]

PhD thesis, 1996

The Multipath Architecture for Prolog Programs.

[BibT_eX]

[DOI]

E. Elias

Comput. J., 1996

1995

Exploiting path parallelism in logic programming.

[BibT_eX]

[DOI]

Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing (PDP '95), 1995

1994

The Multipath Parallel Execution Model for Prolog.

[BibT_eX]

Proceedings of the First International Symposium on Parallel Symbolic Computation, 1994

A Partial Breadth-First Execution Model for Prolog.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Conference on Tools with Artificial Intelligence, 1994

Combining depth-first and breadth-first search in Prolog execution.

[BibT_eX]

Proceedings of the 1994 Joint Conference on Declarative Programming, 1994

1993

MEM: A new execution model for Prolog.

[BibT_eX]

[DOI]