Carlos Silva Cárdenas

Orcid: 0000-0003-4653-0915

According to our database1, Carlos Silva Cárdenas authored at least 14 papers between 2007 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
A New Linear Model for the Calculation of Routing Metrics in 802.11s Using ns-3 and RStudio.
Comput., August, 2023

Electrical and Physical Evaluation of Logic Network Generation Methods for SCCG.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

2021
A Low-Power Elliptic Curve Processor for WISP.
Proceedings of the 19th IEEE International New Circuits and Systems Conference, 2021

2019
Exploring area and total wirelength using a cell merging technique.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

A Flexible UVM-Based Verification Framework Reusable with Avalon, AHB, AXI and Wishbone Bus Interfaces for an AES Encryption Module.
Proceedings of the IEEE Latin American Test Symposium, 2019

A Dependency-Free Real-Time UHD Architecture for the Initial Stage of HEVC Motion Estimation.
Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019

2018
Robust Functional Verification Framework Based in UVM Applied to an AES Encryption Module.
Proceedings of the 2018 New Generation of CAS, 2018

Alternative functional verification methodology for low and medium level designs (Applied to an AES encryption module).
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018

QoS Policies to Improve Performance in Academic Campus and SDN Networks.
Proceedings of the 10th IEEE Latin-American Conference on Communications, 2018

2017
Implementation and testing of IPv6 transition mechanisms.
Proceedings of the 9th IEEE Latin-American Conference on Communications, 2017

2016
A CMOS implementation of the discrete time nonlinear energy operator based on a transconductor-squarer circuit.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

A highly parallel 4K real-time HEVC fractional motion estimation architecture for FPGA implementation.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2012
RAR: Risk Aware Revocation Mechanism for Vehicular Networks.
Proceedings of the 75th IEEE Vehicular Technology Conference, 2012

2007
CMOS encoder for scale-independent pattern recognition.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007


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