Ricardo Augusto da Luz Reis

Affiliations:
  • Federal University of Rio Grande do Sul, Porto Alegre, Brazil


According to our database1, Ricardo Augusto da Luz Reis authored at least 318 papers between 1998 and 2022.

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Bibliography

2022
The Impact of Soft Errors in Memory Units of Edge Devices Executing Convolutional Neural Networks.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Impact of Thread Parallelism on the Soft Error Reliability of Convolution Neural Networks.
Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022

Physical Design Optimization, From Past to Future.
Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

A Lifetime of Physical Design Automation and EDA Education: ISPD 2022 Lifetime Achievement Award Bio.
Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

2021
An Extensive Soft Error Reliability Analysis of a Real Autonomous Vehicle Software Stack.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Applying Lightweight Soft Error Mitigation Techniques to Embedded Mixed Precision Deep Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Evaluation of the soft error assessment consistency of a JIT-based virtual platform simulator.
IET Comput. Digit. Tech., 2021

Exploring a New Tool for Automatic Layout Synthesis for FDSOI 28 nm.
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021

Exploring Gate Mapping and Transistor Sizing to Improve Radiation Robustness: A C17 Benchmark Case-study.
Proceedings of the 22nd IEEE Latin American Test Symposium, 2021

SET Mitigation Techniques on Mirror Full Adder at 7 nm FinFET Technology.
Proceedings of the 22nd IEEE Latin American Test Symposium, 2021

Benchmarking Open Access VLSI Partitioning Tools.
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021

Current Behavior on Process Variability Aware FinFET Inverter Designs.
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021

Voltage Scaling Influence on the Soft Error Susceptibility of a FinFET-based Circuit.
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021

The Impact of Precision Bitwidth on the Soft Error Reliability of the MobileNet Network.
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021

Sensitivity of FinFET Adders to PVT Variations and Sleep Transistor as a Mitigation Strategy.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2021

2020
Multi-Level Design Influences on Robustness Evaluation of 7nm FinFET Technology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

On the superiority of modularity-based clustering for determining placement-relevant clusters.
Integr., 2020

Security Issues in the Design of Chips for IoT.
Proceedings of the 6th IEEE World Forum on Internet of Things, 2020

RAT: A Lightweight System-level Soft Error Mitigation Technique.
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020

RAT: A Lightweight Architecture Independent System-Level Soft Error Mitigation Technique.
Proceedings of the VLSI-SoC: Design Trends, 2020

Fast and Scalable I/O Pin Assignment with Divide-and-Conquer and Hungarian Matching.
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020

Mitigation Effects of Decoupling Cells on Full Adders Process Variability.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

Circuit Level Design Methods to Mitigate Soft Errors.
Proceedings of the IEEE Latin-American Test Symposium, 2020

Work-Function Fluctuation Impact on the SET Response of FinFET-based Majority Voters.
Proceedings of the IEEE Latin-American Test Symposium, 2020

Gate Sizing for Power-Delay Optimization at Transistor-level Monolithic 3D-Integrated Circuits.
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020

Pros and Cons of ST and SIG FinFET Inverters for Low Power Designs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Mirror Full Adder SET Susceptibility on 7nm FinFET Technology.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

Soft Error Reliability Assessment of Neural Networks on Resource-constrained IoT Devices.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

Contributions to OpenROAD from Abroad: Experiences and Learnings : Invited Paper.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Hardware Architecture for the Regular Interpolation Filter of the AV1 Video Coding Standard.
Proceedings of the 28th European Signal Processing Conference, 2020

Soft Error Reliability Using Virtual Platforms - Early Evaluation of Multicore Systems
Springer, ISBN: 978-3-030-55703-4, 2020

2019
Using Machine Learning Techniques to Evaluate Multicore Soft Error Reliability.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A New Nonlinear Global Placement for FPGAs: The Chaotic Place.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Transistor Count Reduction by Gate Merging.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Exploiting memory allocations in clusterised many-core architectures.
IET Comput. Digit. Tech., 2019

Circuit-Level Techniques to Mitigate Process Variability and Soft Errors in FinFET Designs.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Exploration of Techniques to Assess Soft Errors in Multicore Architectures.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Robust FinFET Schmitt Trigger Designs for Low Power Applications.
Proceedings of the VLSI-SoC: New Technology Enabler, 2019

Robustness and Minimum Energy-Oriented FinFET Design.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Minimum Energy FinFET Schmitt Trigger Design Considering Process Variability.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Netlist Optimization by Gate Merging.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Impact of Process Variability and Single Event Transient on FinFET Technology.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Evaluation of SET under Process Variability on FinFET Multi-level Design.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Process Variability Impact on the SET Response of FinFET Multi-level Design.
Proceedings of the VLSI-SoC: New Technology Enabler, 2019

Non-intrusive Fault Injection Techniques for Efficient Soft Error Vulnerability Analysis.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Efficient Soft Error Vulnerability Analysis Using Non-intrusive Fault Injection Techniques.
Proceedings of the VLSI-SoC: New Technology Enabler, 2019

Soft Error Reliability Analysis of Autonomous Vehicles Software Stack.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Exploring area and total wirelength using a cell merging technique.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Cryptography by Synchronization of Hopfield Neural Networks that Simulate Chaotic Signals Generated by the Human Body.
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019

Exploring Schmitt Trigger Circuits for Process Variability Mitigation.
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019

Process Variability Challenges for Radiation Mitigation Techniques on 16nm.
Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019

Clip Clustering for Early Lithographic Hotspot Classification.
Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019

Tackling the Drawbacks of a Lagrangian Relaxation Based Discrete Gate Sizing Algorithm.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Evaluation of Compilers Effects on OpenMP Soft Error Resiliency.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Challenges in the Design of Integrated Systems for IoT.
Proceedings of the Internet of Things. A Confluence of Many Disciplines, 2019

Sleep Transistors to Improve the Process Variability and Soft Error Susceptibility.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

FinFET Variability and Near-threshold operation: Impact on Full Adders design using XOR Blocks.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

FBM: A Simple and Fast Algorithm for Placement Legalization.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Proposal and Evaluation of Pin Access Algorithms for Detailed Routing.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Finding placement-relevant clusters with fast modularity-based clustering.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
Impact of different transistor arrangements on gate variability.
Microelectron. Reliab., 2018

Evaluation of variability using Schmitt trigger on full adders layout.
Microelectron. Reliab., 2018

Analysis of 6 T SRAM cell in sub-45 nm CMOS and FinFET technologies.
Microelectron. Reliab., 2018

Evaluating the Impact of Process Variability and Radiation Effects on Different Transistor Arrangements.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

Evaluation of Compiler Optimization Flags Effects on Soft Error Resiliency.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

A Design Patterns-Based Middleware for Multiprocessor Systems-on-Chip.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

Reducing the amount of transistors by gate merging.
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018

gem5-FIM: a flexible and scalable multicore soft error assessment framework to early reliability design space explorations.
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018

A nonlinear placement for FPGAs: The chaotic place.
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018

An automated methodology to fix electromigration violations on a customized design flow.
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018

Pros and Cons of Schmitt Trigger Inverters to Mitigate PVT Variability on Full Adders.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Exploring the Impact of Soft Errors on NoC-based Multiprocessor Systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Strategies for Reducing Power Consumption and Increasing Reliability in IoT.
Proceedings of the Internet of Things. Information Processing in an Increasingly Connected World, 2018

Impact of Near-Threshold and Variability on 7nm FinFET XOR Circuits.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Exploring Multi-level Design to Mitigate Variability and Radiation Effects on 7nm FinFET Logic Cells.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Extensive evaluation of programming models and ISAs impact on multicore soft error reliability.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Evaluation of heavy-ion impact in bulk and FDSOI devices under ZTC condition.
Microelectron. Reliab., 2017

Evaluation of radiation-induced soft error in majority voters designed in 7 nm FinFET technology.
Microelectron. Reliab., 2017

VLSI-SoC: An Enduring Tradition.
Proceedings of the VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things, 2017

Evaluation of multicore systems soft error reliability using virtual platforms.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

Process and temperature impact on single-event transients in 28nm FDSOI CMOS.
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

Radiation sensitivity of XOR topologies in multigate technologies under voltage variability.
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

Rsyn: An Extensible Physical Synthesis Framework.
Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

Robustness of Sub-22nm multigate devices against physical variability.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Publish-subscribe programming for a NoC-based multiprocessor system-on-chip.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Impact of schmitt trigger inverters on process variability robustness of 1-Bit full adders.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

Investigating parallel TMR approaches and thread disposability in Linux.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

UFRGSPlace: Routability driven FPGA placement algorithm for heterogeneous FPGAs.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

A cell clustering technique to reduce transistor count.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

Temperature dependence and ZTC bias point evaluation of sub 20nm bulk multigate devices.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

SET response of FinFET-based majority voter circuits under work-function fluctuation.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

2016
Cell-Internal Electromigration: Analysis and Pin Placement Based Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

FDSOI and Bulk CMOS SRAM Cell Resilience to Radiation Effects.
Microelectron. Reliab., 2016

Permanent and single event transient faults reliability evaluation EDA tool.
Microelectron. Reliab., 2016

Selected Articles from the 6th International Workshop on CMOS Variability, Salvador, Bahia, Brazil, September 1-4, 2015.
J. Low Power Electron., 2016

Challenges of cell selection algorithms in industrial high performance microprocessor designs.
Integr., 2016

Leakage current analysis in static CMOS logic gates for a transistor network design approach.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

Improving placement algorithms by using visualization tools.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

Reducing the number of transistors with gate clustering.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

Routing-Aware Incremental Timing-Driven Placement.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Cell Selection for High-Performance Designs in an Industrial Design Flow.
Proceedings of the 2016 on International Symposium on Physical Design, 2016

Drive Strength Aware Cell Movement Techniques for Timing Driven Placement.
Proceedings of the 2016 on International Symposium on Physical Design, 2016

FinFET cells with different transistor sizing techniques against PVT variations.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Electromigration aware circuits by using special signal non-default routing rules.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Impact of variability effects on FinFET transistors and combinational cells.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Geometric variability impact on 7nm Trigate combinational cells.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

DHyANA: A NoC-based neural network hardware architecture.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Quadratic timing objectives for incremental timing-driven placement optimization.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Extending FreeRTOS to support dynamic and distributed mapping in multiprocessor systems.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015
Impact of PVT variability on 20 nm FinFET standard cells.
Microelectron. Reliab., 2015

Impact of dynamic voltage scaling and thermal factors on SRAM reliability.
Microelectron. Reliab., 2015

An Incremental Timing-Driven flow using quadratic formulation for detailed placement.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Jezz: An Effective Legalization Algorithm for Minimum Displacement.
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015

Energy-efficient Level Shifter topology.
Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015

Reusing smaller optimized FFT blocks for the realization of larger power-efficient radix-2 FFTs.
Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015

Multiple fault injection platform for SRAM-based FPGA based on ground-level radiation experiments.
Proceedings of the 16th Latin-American Test Symposium, 2015

Overhead for independent net approach for Global Routing.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

Reducing the signal Electromigration effects on different logic gates by cell layout optimization.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

Efficient emulation of quantum circuits on classical hardware.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

Modeling the impact of heavy ion on FDSOI NanoCMOS.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

Analyzing the Impact of Frequency and Diverse Path Delays in the Time Vulnerability Factor of Master-Slave D Flip-Flops.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

A mixed cells physical design approach.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Low Latency FPGA Implementation of Izhikevich-Neuron Model.
Proceedings of the System Level Design from HW/SW to Memory for Embedded Systems, 2015

Process variability in FinFET standard cells with different transistor sizing techniques.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

Impact of dynamic voltage scaling and thermal factors on FinFET-based SRAM reliability.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

Impact on performance, power, area and wirelength using electromigration-aware cells.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

Bulk and FDSOI Sub-micron CMOS transistors resilience to single-event transients.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

A fast and scalable fault injection framework to evaluate multi/many-core soft error reliability.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

Gate sizing and threshold voltage assignment for high performance microprocessor designs.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Energy efficient frame-level redundancy scrubbing technique for SRAM-based FPGAs.
Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015

Graphite-based heat spreaders for hotspot mitigation in 3D ICs.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

2014
Effective Method for Simultaneous Gate Sizing and $V$ th Assignment Using Lagrangian Relaxation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Predictive evaluation of electrical characteristics of sub-22 nm FinFET technologies under device geometry variations.
Microelectron. Reliab., 2014

Voltage scaling and aging effects on soft error rate in SRAM-based FPGAs.
Microelectron. Reliab., 2014

Power dissipation effects on 28nm FPGA-based System on Chips neutron sensitivity.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

Automated Synthesis of Cell Libraries for Asynchronous Circuits.
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

Evaluating the impact of environment and physical variability on the ION current of 20nm FinFET devices.
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014

Fast energy evaluation of embedded applications for many-core systems.
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014

Bulk and FDSOI SRAM resiliency to radiation effects.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

Soft error rate in SRAM-based FPGAs under neutron-induced and TID effects.
Proceedings of the 15th Latin American Test Workshop, 2014

Automatic layout synthesis with ASTRAN applied to asynchronous cells.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

Exploring more efficient architectures for Multiple Dynamic Supply Voltage designs.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

Comparing high-performance cells in CMOS bulk and FinFET technologies.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

Simultaneous Two-Dimensional Cell Layout Compaction Using MILP with ASTRAN.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Perfomance Improvement with Dedicated Transistor Sizing for MOSFET and FinFET Devices.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Thermal impact of 3D stacking and die thickness: Analysis and characterization of a memory-on-logic 3D circuit.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Analyzing the electromigration effects on different metal layers and different wire lengths.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Impact of gate workfunction fluctuation on FinFET standard cells.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

A systematic approach for analyzing and optimizing cell-internal signal electromigration.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

A tool to simulate optical lithography in nanoCMOs.
Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2014

A set of Virtual Instruments to simulate radiation effects in CMOS circuits.
Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2014

A design flow for physical synthesis of digital cells with ASTRAN.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Aging and voltage scaling impacts under neutron-induced soft error rate in SRAM-based FPGAs.
Proceedings of the 19th IEEE European Test Symposium, 2014

Thermal modeling methodology for efficient system-level thermal analysis.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

Thermal performance of 3D ICs: Analysis and alternatives.
Proceedings of the 2014 International 3D Systems Integration Conference, 2014

Using TSVs for thermal mitigation in 3D circuits: Wish and truth.
Proceedings of the 2014 International 3D Systems Integration Conference, 2014

2013
Revisiting automated physical synthesis of high-performance clock networks.
ACM Trans. Design Autom. Electr. Syst., 2013

GR-PA: A cost pre-allocation model for global routing.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Global routing congestion reduction with cost allocation look-ahead.
Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013

FinFET basic cells evaluation for regular layouts.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

Using electromagnetic emanations for variability characterization in Flash-based FPGAs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

A yield-driven regular layout synthesis.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Message from the general and program chairs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Simultaneous gate sizing and Vth assignment using Lagrangian Relaxation and delay sensitivities.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Simultaneous gate sizing and Vt assignment using Fanin/Fanout ratio and Simulated Annealing.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A novel approach to reduce power consumption in level shifter for Multiple Dynamic Supply Voltage.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

Instruction-driven timing CPU model for efficient embedded software development using OVP.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

Combining fault tolerance and serialization effort to improve yield in 3D Networks-on-Chip.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

System-level thermal modeling for 3D circuits: Characterization with a 65nm memory-on-logic circuit.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012
High-performance clock mesh optimization.
ACM Trans. Design Autom. Electr. Syst., 2012

Posicionamento de Circuitos 3D Considerando o Planejamento de 3D-Vias.
RITA, 2012

Multi-bit flip-flop usage impact on physical synthesis.
Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012

Transistor sizing and gate sizing using geometric programming considering delay minimization.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012

SET susceptibility estimation of clock tree networks from layout extraction.
Proceedings of the 13th Latin American Test Workshop, 2012

Simulation of SET faults in a voltage controlled oscillator.
Proceedings of the 13th Latin American Test Workshop, 2012

Soft-Error Probability Due to SET in Clock Tree Networks.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Efficient area and power multiplication part of FFT based on twiddle factor decomposition.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011
A Low-Cost Solution for Deploying Processor Cores in Harsh Environments.
IEEE Trans. Ind. Electron., 2011

Quadratic placement with single-iteration linear system solver.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

Gate Sizing Minimizing Delay and Area.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Design automation of transistor networks, a new challenge.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Power consumption in transistor networks versus in standard cells.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

Combination of constant matrix multiplication and gate-level approaches for area and power efficient hybrid radix-2 DIT FFT realization.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

Design Tools and Methods for Chip Physical Design.
Proceedings of the Multiprocessor System-on-Chip - Hardware Design and Tool Integration., 2011

2010
Asynchronous circuits as alternative for mitigation of long-duration transient faults in deep-submicron technologies.
Microelectron. Reliab., 2010

3D-Via Driven Partitioning for 3D VLSI Integrated Circuits.
CLEI Electron. J., 2010

Low-sensitivity to process variations aging sensor for automotive safety-critical applications.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Logical Core Algorithm: Improving Global Placement.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

A Mesh-Buffer Displacement Optimization Strategy.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Predictive error detection by on-line aging monitoring.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

Evaluating transient-fault effects on traditional C-element's implementations.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

Design and verification of a layer-2 Ethernet MAC classification engine for a Gigabit Ethernet switch.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Routing algorithms performance in different routing scopes.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

A study on layout quality of automatic generated cells.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Radix-2 Decimation in Time (DIT) FFT implementation based on a Matrix-Multiple Constant multiplication approach.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

The Fidelity Property of the Elmore Delay Model in actual comparison of routing algorithms.
Proceedings of the 28th International Conference on Computer Design, 2010

Non-uniform clock mesh optimization with linear programming buffer insertion.
Proceedings of the 47th Design Automation Conference, 2010

2009
Maze Routing Steiner Trees With Delay Versus Wire Length Tradeoff.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Design of a soft-error robust microprocessor.
Microelectron. J., 2009

Challenges and Emerging Technologies for System Integration beyond the End of the Roadmap of Nano-CMOS.
Proceedings of the VLSI-SoC: Technologies for Systems Integration, 2009

Protecting digital circuits against hold time violation due to process variability.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

Resource-and-time-aware test strategy for configurable quaternary logic blocks.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

Analysis of Power Consumption Using a New Methodology for the Capacitance Modeling of Complex Logic Gates.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

Built-in aging monitoring for safety-critical applications.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

Comparing transient-fault effects on synchronous and on asynchronous circuits.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

A cells and I/O pins partitioning refinement algorithm for 3D VLSI circuits.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

On the accuracy of Elmore-based Delay Models.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

An automated design methodology for layout generation targeting power leakage minimization.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

An On-board Data-Handling Computer for Deep-Space Exploration Built Using Commercial-Off-the-Shelf SRAM-Based FPGAs.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

A low-cost SEE mitigation solution for soft-processors embedded in Systems on Pogrammable Chips.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Probabilistic Approach for Yield Analysis of Dynamic Logic Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

A novel scheme to reduce short-circuit power in mesh-based clock architectures.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

A New Clock Mesh Buffer Sizing Methodology for Skew and Power Reduction.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Design procedure for DVB-T receivers large tuning range LP filter.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
On the Evolution of Remote Laboratories for Prototyping Digital Electronic Systems.
IEEE Trans. Ind. Electron., 2007

Técnicas probabilísticas para análise de yield em nível elétrico usando propagação de erros e derivadas numéricas.
RITA, 2007

A Case Study on Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis.
J. Electron. Test., 2007

Memory-efficient multithreaded code generation from Simulink for heterogeneous MPSoC.
Des. Autom. Embed. Syst., 2007

Statistical Analysis of Normality of Systematic and Random Variability of Flip-Flop Race Immunity in 130nm and 90nm CMOS Technologies.
Proceedings of the VLSI-SoC: Advanced Topics on Systems on a Chip, 2007

Statistical analysis of systematic and random variability of flip-flop race immunity in 130nm and 90nm CMOS technologies.
Proceedings of the IFIP VLSI-SoC 2007, 2007

Efficient timing closure with a transistor level design flow.
Proceedings of the IFIP VLSI-SoC 2007, 2007

Statistical and Numerical Approach for a Computer efficient circuit yield analysis.
Proceedings of the VLSI-SoC: Advanced Topics on Systems on a Chip, 2007

Obtaining delay distribution of dynamic logic circuits by error propagation at the electrical level.
Proceedings of the IFIP VLSI-SoC 2007, 2007

Reducing fine-grain communication overhead in multithread code generation for heterogeneous MPSoC.
Proceedings of the 10th International Workshop on Software and Compilers for Embedded Systems, 2007

Cell placement on graphics processing units.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

An Educational Tool for Design Automation of CMOS Cells.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007

A CAL Tool to Aid the Understanding of Logic Synthesis.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007

Inserting Data Encoding Techniques into NoC-Based Systems.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

3D-Vias Aware Quadratic Placement for 3D VLSI Circuits.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Yield Analysis by Error Propagation Using Numerical Derivatives Considering WD and D2D variations.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Maze routing steiner trees with effective critical sink optimization.
Proceedings of the 2007 International Symposium on Physical Design, 2007

A 3D-Via Legalization Algorithm for 3D VLSI Circuits and its Impact on Wire Length.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Reducing the Power Consumption in Networks-on-Chip through Data Coding Schemes.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

Logic and Physical Synthesis of Cell Arrays.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006
A Method for I/O Pins Partitioning Targeting 3D VLSI Circuits.
Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006

An Algorithm for I/O Partitioning Targeting 3D Circuits and Its Impact on 3D-Vias.
Proceedings of the IFIP VLSI-SoC 2006, 2006

Quadratic placement for 3d circuits using z-cell shifting, 3d iterative refinement and simulated annealing.
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006

Design at high level of a robust 8-bit microprocessor to soft errors by using only standard gates.
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006

Adaptive Coding in Networks-on-Chip: Transition Activity Reduction Versus Power Overhead of the Codec Circuitry.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Considering Zero-Arrival Time and Block-Arrival Time in Hierarchical Functional Timing Analysis.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Evaluating the Impact of Data Encoding Techniques on the Power Consumption in Networks-on-Chip.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

A Regular Layout Approach for ASICs.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Channel based routing in channel-less circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis: A Case Study.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

Design of a Robust 8-Bit Microprocessor to Soft Errors.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

orBDDs Direct Mapping for Structured Logic Circuits.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

Unbalacing the I/O Pins Partitioning for Minimizing Inter-Tier Vias in 3D VLSI Circuits.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

A New Transistor-Level Layout Generation Strategy for Static CMOS Circuits.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
Desenvolvimento de Técnicas de Tolerância à Falhas para Componentes Programáveis por SRAM.
RITA, 2005

An Automatic Technique for Optimizing Reed-Solomon Codes to Improve Fault Tolerance in Memories.
IEEE Des. Test Comput., 2005

A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures.
Proceedings of the VLSI-SoC: From Systems To Silicon, 2005

Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs.
Proceedings of the VLSI-SoC: From Systems To Silicon, 2005

A Transistor Placement Technique Using Genetic Algorithm and Analytical Programming.
Proceedings of the VLSI-SoC: From Systems To Silicon, 2005

Mapping embedded systems onto NoCs: the traffic effect on dynamic energy estimation.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005

Designing Low-Power Embedded Software for Mass-Produced Microprocessor by Using a Loop Table in On-Chip Memory.
Proceedings of the Integrated Circuit and System Design, 2005

Incremental timing optimization for automatic layout generation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

On Implementing a Soft Error Hardening Technique by Using an Automatic Layout Generator: Case Study.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

Blue Macaw: A Didactic Placement Tool Using Simulated Annealing.
Proceedings of the New Trends and Technologies in Computer-Aided Learning for Computer-Aided Design, 2005

TOC-BISR: A Self-Repair Scheme for Memories in Embedded Systems.
Proceedings of the From Specification to Embedded Systems Application [International Embedded Systems Symposium, 2005

Comparing high-level modeling approaches for embedded system design.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Um Framework de Apoio à Colaboração no Projeto Distribuído de Sistemas Integrados.
RITA, 2004

Designing Fault-Tolerant Techniques for SRAM-Based FPGAs.
IEEE Des. Test Comput., 2004

Lookup-based Remote Laboratory for FPGA Digital Design Prototyping.
Proceedings of the e-learning and Virtual and Remote Laboratories, 2004

Accurate capture of timing parameters in inductively-coupled on-chip interconnects.
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

A New Transistor Folding Algorithm Applied to an Automatic Full-Custom Layout Generation Tool.
Proceedings of the Integrated Circuit and System Design, 2004

Requirements for Computer-Aided Learning from the Point of View of Electronic Design.
Proceedings of the EDUTECH, 2004

Design of Very Deep Pipelined Multipliers for FPGAs.
Proceedings of the 2004 Design, 2004

Physical design methodologies for performance predictability and manufacturability.
Proceedings of the First Conference on Computing Frontiers, 2004

Designing and testing fault-tolerant techniques for SRAM-based FPGAs.
Proceedings of the First Conference on Computing Frontiers, 2004

2003
A multiple bit upset tolerant SRAM memory.
ACM Trans. Design Autom. Electr. Syst., 2003

Quadrature sampling schemes with improved image rejection.
IEEE Trans. Circuits Syst. II Express Briefs, 2003

A Novel full Automatic Layout Generation Strategy for Static CMOS Circuits.
Proceedings of the VLSI-SOC: From Systems to Chips, 2003

A New Macro-cell Generation Strategy for three metal layer CMOS Technologies.
Proceedings of the IFIP VLSI-SoC 2003, 2003

A study on the performance of fast initial placement algorithms.
Proceedings of the IFIP VLSI-SoC 2003, 2003

A Transistor Sizing Method Applied to an Automatic Layout Generation Tool.
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

Improving Simulated Annealing Placement by Applying Random and Greedy Mixed Perturbations.
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

Improving Critical Path Identification in Functional Timing Analysis.
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

Power and Timing Driven Physical Design Automation.
Proceedings of the Integrated Circuit and System Design, 2003

Reducing Authoring Costs of Online Training in Microelectronics Design by Reusing Design Documentation Content.
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

A Visual Simulation Tool at Layout Level.
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

Plic-Plac: a novel constructive algorithm for placement.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Reducing pin and area overhead in fault-tolerant FPGA-based designs.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

Supporting Consistency Control between Functional and Structural Views in Interface-based Design Models.
Proceedings of the Forum on specification and Design Languages, 2003

A Low Device Occupation IP to Implement Rijndael Algorithm.
Proceedings of the 2003 Design, 2003

Ubiquitous Access to Reconfigurable Hardware: Application Scenarios and Implementation Issues.
Proceedings of the 2003 Design, 2003

Designing fault tolerant systems into SRAM-based FPGAs.
Proceedings of the 40th Design Automation Conference, 2003

2002
Finding the Critical Delay of Combinational Blocks by Floating Vector Simulation and Path Tracing.
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002

Collaborative Design Using a Shared Object Spaces Infrastructure.
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002

An IP of an Advanced Encryption Standard for Altera" Devices.
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002

A LEGAL Algorithm Following Global Routing.
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002

Analyzing Area and Performance Penalty of Protecting Different Digital Modules with Hamming Code and Triple Modular Redundancy.
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002

Injecting Multiple Upsets in a SEU Tolerant 8051 Micro-Controller.
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002


Comparative Analysis and Application of Data Repository Infrastructure for Collaboration-Enabled Distributed Design Environments.
Proceedings of the 2002 Design, 2002

2001
Análise de Timing Funcional de Circuitos VLSI Contendo Portas Complexas.
RITA, 2001

3D integrated circuit layout visualization using VRML.
Future Gener. Comput. Syst., 2001

Synthesis of an 8051-Like Micro-Controller Tolerant to Transient Faults.
J. Electron. Test., 2001

Jale3D - Platform-independent IC/MEMS Layout Edition Tool.
Proceedings of the 14th Annual Symposium on Integrated Circuits and Systems Design, 2001

Interconnection Length Estimation at Logic-Level.
Proceedings of the 14th Annual Symposium on Integrated Circuits and Systems Design, 2001

LEGAL: An Algorithm for Simultaneous Net Routing.
Proceedings of the 14th Annual Symposium on Integrated Circuits and Systems Design, 2001

Distributed Collaborative Design over Cave2 Framework.
Proceedings of the SOC Design Methodologies, 2001

2000
Specification and design of an Ethernet Interface soft IP.
J. Braz. Comput. Soc., 2000

Admissibility Proofs for the LCS* Algorithm.
Proceedings of the Advances in Artificial Intelligence, 2000

Designing a Radiation Hardened 8051-Like Micro-Controller.
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000

Net by Net Routing with a New Path Search Algorithm.
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000

From a Hyperdocument-Centric to an Object-Oriented Approach for the Cave Project.
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000

ATG-Based Timing Analysis of Circuits Containing Complex Gates.
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000

WTROPIC: A WWW-Based Macro-Cell Generator.
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000

LASCA-Interconnect Parasitic Extraction Tool for Deep-Submicron IC Design.
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000

SisECO: Design of an Echo-Canceling IC for Base Band Modems.
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000

Structuring Web course pages as Automata: revising concepts.
Proceedings of the Computer-Assisted Information Retrieval (Recherche d'Information et ses Applications), 2000

A frame stream controller IP.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999
VRML and Microelectronics Education.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 1999

Microelectronics Education Using WWW.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 1999

Designing a Mask Programmable Matrix for Sequential Circuits.
Proceedings of the VLSI: Systems on a Chip, 1999

1998
An Improved Path Enumeration Method Considering Different Fall and Rise Gate Delays.
Proceedings of the 11th Annual Symposium on Integrated Circuits Design, 1998

A Case Study for a WWW based CAD Framework.
Proceedings of the 11th Annual Symposium on Integrated Circuits Design, 1998

Microelectronics Education using WWW and CAD Tools.
Proceedings of the 11th Annual Symposium on Integrated Circuits Design, 1998


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