Cecil Accetti

Orcid: 0000-0003-2985-2293

Affiliations:
  • Shanghai Jiaotong University, School of Electronic Information and Electrical Engineering, China


According to our database1, Cecil Accetti authored at least 8 papers between 2012 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

Online presence:

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Bibliography

2022
Structured Combinators for Efficient Graph Reduction.
IEEE Comput. Archit. Lett., 2022

Architectural Support for Functional Programming.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

2020
A Platform for Full-Stack Functional Programming.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2018
An FPGA-Based RFID Baseband Processor Using a RISC-V Platform.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

A 974GOPS/W Multi-level Parallel Architecture for Binary Weight Network Acceleration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
A 42fps full-HD ORB feature extraction accelerator with reduced memory overhead.
Proceedings of the International Conference on Field Programmable Technology, 2017

2016
Oolong: A Baseband processor extension to the RISC-V ISA.
Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

2012
FPGA-based digital direct-conversion transceiver for Nuclear Magnetic Resonance Systems.
Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012


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