Chaeryung Park

According to our database, Chaeryung Park authored at least 5 papers between 1993 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

Placement-Aware 3D Net-to-Pad Assignment for Array-Style Hybrid Bonding 3D ICs.

Pruek Vanna-Iampikul, Jun-Sik Yoon, Chaeryung Park, Gary Yeap, Sung Kyu Lim

Proceedings of the 2025 International Symposium on Physical Design, 2025

2000

An Integrated Approach to Data Path Synthesis for Behavioral-level Power Optimization.

Chaeryung Park, Taewhan Kim, C. L. Liu

VLSI Design, 2000

1999

An efficient data path synthesis algorithm for behavioral-level power optimization.

Chaeryung Park, Taewhan Park, C. L. Liu

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1998

Register Allocation - A Hierarchical Reduction Approach.

Chaeryung Park, Taewhan Kim, C. L. Liu

J. VLSI Signal Process., 1998

1993

Register allocation for data flow graphs with conditional branches and loops.

Chaeryung Park, Taewhan Kim, C. L. Liu

Proceedings of the European Design Automation Conference 1993, 1993