Jun-Sik Yoon
Orcid: 0000-0002-3132-4556Affiliations:
- Pohang University of Science and Technology, South Korea
According to our database1,
Jun-Sik Yoon
authored at least 14 papers
between 2019 and 2023.
Collaborative distances:
Collaborative distances:
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on orcid.org
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Bibliography
2023
Holistic Optimization of Trap Distribution for Performance/Reliability in 3-D NAND Flash Using Machine Learning.
IEEE Access, 2023
A Comparative Study on Front-Side, Buried and Back-Side Power Rail Topologies in 3nm Technology Node.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023
2022
DC Performance Variations by Grain Boundary in Source/Drain Epitaxy of Sub-3-nm Nanosheet Field-Effect Transistors.
IEEE Access, 2022
Extraction of Device Structural Parameters Through DC/AC Performance Using an MLP Neural Network Algorithm.
IEEE Access, 2022
2021
Digital/Analog Performance Optimization of Vertical Nanowire FETs Using Machine Learning.
IEEE Access, 2021
Monolithic 3D 6T-SRAM Based on Newly Designed Gate and Source/Drain Bottom Contact Schemes.
IEEE Access, 2021
Analysis of TSV-Induced Mechanical Stress and Electrical Noise Coupling in Sub 5-nm Node Nanosheet FETs for Heterogeneous 3D-ICs.
IEEE Access, 2021
2020
A Novel Sub-5-nm Node Dual-Workfunction Folded Cascode Nanosheet FETs for Low Power Mobile Applications.
IEEE Access, 2020
Device Design Guideline of 5-nm-Node FinFETs and Nanosheet FETs for Analog/RF Applications.
IEEE Access, 2020
Comprehensive Analysis of Source and Drain Recess Depth Variations on Silicon Nanosheet FETs for Sub 5-nm Node SoC Application.
IEEE Access, 2020
IEEE Access, 2020
2019
Source/Drain Patterning FinFETs as Solution for Physical Area Scaling Toward 5-nm Node.
IEEE Access, 2019
Bottom Oxide Bulk FinFETs Without Punch-Through-Stopper for Extending Toward 5-nm Node.
IEEE Access, 2019
Punch-Through-Stopper Free Nanosheet FETs With Crescent Inner-Spacer and Isolated Source/Drain.
IEEE Access, 2019