Sung Kyu Lim

According to our database1, Sung Kyu Lim authored at least 217 papers between 1997 and 2019.

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Bibliography

2019
System-Level Power Delivery Network Analysis and Optimization for Monolithic 3-D ICs.
IEEE Trans. VLSI Syst., 2019

Entropy Production-Based Full-Chip Fatigue Analysis: From Theory to Mobile Applications.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

A Logic-on-Memory Processor-System Design With Monolithic 3-D Technology.
IEEE Micro, 2019

Tier Partitioning and Flip-flop Relocation Methods for Clock Trees in Monolithic 3D ICs.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

Logic Monolithic 3D ICs: PPA Benefits and EDA Tools Necessary.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Built-in Self-Test for Inter-Layer Vias in Monolithic 3D ICs.
Proceedings of the 24th IEEE European Test Symposium, 2019

RTL-to-GDS Tool Flow and Design-for-Test Solutions for Monolithic 3D ICs.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Architecture, Chip, and Package Co-design Flow for 2.5D IC Design Enabling Heterogeneous IP Reuse.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Power, Performance, and Area Benefit of Monolithic 3D ICs for On-Chip Deep Neural Networks Targeting Speech Recognition.
JETC, 2018

A Twin Memristor Synapse for Spike Timing Dependent Learning in Neuromorphic Systems.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018

Compact-2D: A Physical Design Methodology to Build Commercial-Quality Face-to-Face-Bonded 3D ICs.
Proceedings of the 2018 International Symposium on Physical Design, 2018

Road to High-Performance 3D ICs: Performance Optimization Methodologies for Monolithic 3D ICs.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018

Area-efficient and low-power face-to-face-bonded 3D liquid state machine design.
Proceedings of the International Conference on Computer-Aided Design, 2018

In-growth test for monolithic 3D integrated SRAM.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Design and architectural co-optimization of monolithic 3D liquid state machine-based neuromorphic processor.
Proceedings of the 55th Annual Design Automation Conference, 2018

A novel 3D DRAM memory cube architecture for space applications.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Design Methodologies for Low-Power 3-D ICs With Advanced Tier Partitioning.
IEEE Trans. VLSI Syst., 2017

Chain-Based Approach for Fast Through-Silicon-Via Coupling Delay Estimation.
IEEE Trans. VLSI Syst., 2017

Impact and Design Guideline of Monolithic 3-D IC at the 7-nm Technology Node.
IEEE Trans. VLSI Syst., 2017

Full Chip Impact Study of Power Delivery Network Designs in Gate-Level Monolithic 3-D ICs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Tier Degradation of Monolithic 3-D ICs: A Power Performance Study at Different Technology Nodes.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Shrunk-2-D: A Physical Design Methodology to Build Commercial-Quality Monolithic 3-D ICs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

TSV-Based 3-D ICs: Design Methods and Tools.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching Processors.
Sensors, 2017

Bringing 3D ICs to Aerospace: Needs for Design Tools and Methodologies.
J. Inform. and Commun. Convergence Engineering, 2017

Improving Performance under Process and Voltage Variations in Near-Threshold Computing Using 3D ICs.
JETC, 2017

Evaluating online-learning in memristive neuromorphic circuits.
Proceedings of the Neuromorphic Computing Symposium, 2017

Full chip power benefits with negative capacitance FETs.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

Transistor-level monolithic 3D standard cell layout optimization for full-chip static power integrity.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

Monolithic 3D IC designs for low-power deep neural networks targeting speech recognition.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

Frequency and time domain analysis of power delivery network for monolithic 3D ICs.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

Full-chip monolithic 3D IC design and power performance analysis with ASAP7 library: (Invited Paper).
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Design automation and testing of monolithic 3D ICs: Opportunities, challenges, and solutions: (Invited paper).
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

2016
Full-Chip Signal Integrity Analysis and Optimization of 3-D ICs.
IEEE Trans. VLSI Syst., 2016

More Power Reduction With 3-Tier Logic-on-Logic 3-D ICs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Adaptive Regression-Based Thermal Modeling and Optimization for Monolithic 3-D ICs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Design and Analysis of a Stochastic Flash Analog-to-Digital Converter in 3D IC technology for integration with ultrasound transducer array.
Microelectronics Journal, 2016

Exploration of temperature-aware refresh schemes for 3D stacked eDRAM caches.
Microprocessors and Microsystems - Embedded Hardware Design, 2016

Device Coupling Effects of Monolithic 3D Inverters.
J. Inform. and Commun. Convergence Engineering, 2016

Machine Learning Based Variation Modeling and Optimization for 3D ICs.
J. Inform. and Commun. Convergence Engineering, 2016

Fast bidirectional shortest path on GPU.
IEICE Electronic Express, 2016

Guest Editors' Introduction: Advances in 3-D Integrated Circuits, Systems, and CAD Tools - Part 2.
IEEE Design & Test, 2016

Monolithic 3D IC design: Power, performance, and area impact at 7nm.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

How to Cope with Slow Transistors in the Top-tier of Monolithic 3D ICs: Design Studies and CAD Solutions.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Physical Design Solutions to Tackle FEOL/BEOL Degradation in Gate-level Monolithic 3D ICs.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Four-tier Monolithic 3D ICs: Tier Partitioning Methodology and Power Benefit Study.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Tier partitioning strategy to mitigate BEOL degradation and cost issues in monolithic 3D ICs.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

How much cost reduction justifies the adoption of monolithic 3D ICs at 7nm node?
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Cascade2D: A design-aware partitioning approach to monolithic 3D IC with 2D commercial tools.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Match-making for monolithic 3D IC: finding the right technology node.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
Scan Test of Die Logic in 3-D ICs Using TSV Probing.
IEEE Trans. VLSI Syst., 2015

Multi-TSV and E-Field Sharing Aware Full-chip Extraction and Mitigation of TSV-to-Wire Coupling.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Placement-Driven Partitioning for Congestion Mitigation in Monolithic 3D IC Designs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory).
IEEE Trans. Computers, 2015

Full-Chip Power/Performance Benefits of Carbon Nanotube-Based Circuits.
J. Inform. and Commun. Convergence Engineering, 2015

Die-to-Die Parasitic Extraction Targeting Face-to-Face Bonded 3D ICs.
J. Inform. and Commun. Convergence Engineering, 2015

Physical Design and CAD Tools for 3-D Integrated Circuits: Challenges and Opportunities.
IEEE Design & Test, 2015

Guest Editors' Introduction: Advances in 3-D Integrated Circuits, Systems, and CAD Tools.
IEEE Design & Test, 2015

On diagnosable and tunable 3D clock network design for lifetime reliability enhancement.
Proceedings of the 2015 IEEE International Test Conference, 2015

Power benefit study of monolithic 3D IC at the 7nm technology node.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Stacking integration methodologies in 3D IC for 3D ultrasound image processing application: A stochastic flash ADC design case study.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A Novel Entropy Production Based Full-Chip TSV Fatigue Analysis.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Three-Tier 3D ICs for More Power Reduction: Strategies in CAD, Design, and Bonding Selection.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Full-chip Inter-die Parasitic Extraction in Face-to-Face-Bonded 3D ICs.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Tier-partitioning for power delivery vs cooling tradeoff in 3D VLSI for mobile applications.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Low Power Monolithic 3D IC Design of Asynchronous AES Core.
Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015

2014
Backend Dielectric Reliability Full Chip Simulator.
IEEE Trans. VLSI Syst., 2014

Exploiting Die-to-Die Thermal Coupling in 3-D IC Placement.
IEEE Trans. VLSI Syst., 2014

Silicon Effect-Aware Full-Chip Extraction and Mitigation of TSV-to-TSV Coupling.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Electromigration Study for Multiscale Power/Ground Vias in TSV-Based 3-D ICs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

TSV-Aware Interconnect Distribution Models for Prediction of Delay and Power Consumption of 3-D Stacked ICs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Simulation of system backend dielectric reliability.
Microelectronics Journal, 2014

Design Challenges and Solutions for Ultra-High-Density Monolithic 3D ICs.
J. Inform. and Commun. Convergence Engineering, 2014

Research Needs for TSV-Based 3D IC Architectural Floorplanning.
J. Inform. and Commun. Convergence Engineering, 2014

TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC.
Commun. ACM, 2014

Design and CAD methodologies for low power gate-level monolithic 3D ICs.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Full chip impact study of power delivery network designs in monolithic 3D ICs.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

On GPU bus power reduction with 3D IC technologies.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Fast and Accurate Thermal Modeling and Optimization for Monolithic 3D ICs.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Fast and Accurate Full-chip Extraction and Optimization of TSV-to-Wire Coupling.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Power-Performance Study of Block-Level Monolithic 3D-ICs Considering Inter-Tier Performance Variations.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

On Enhancing Power Benefits in 3D ICs: Block Folding and Bonding Styles Perspective.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
IsoNet: Hardware-Based Job Queue Management for Many-Core Architectures.
IEEE Trans. VLSI Syst., 2013

Study of Through-Silicon-Via Impact on the 3-D Stacked IC Layout.
IEEE Trans. VLSI Syst., 2013

Ultrahigh Density Logic Designs Using Monolithic 3-D Integration.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Chip/Package Mechanical Stress Impact on 3-D IC Reliability and Mobility Variations.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Reliable 3-D Clock-Tree Synthesis Considering Nonlinear Capacitive TSV Model With Electrical-Thermal-Mechanical Coupling.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Impact of Mechanical Stress on the Full Chip Timing for Through-Silicon-Via-based 3-D ICs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Design and analysis of ultra low power processors using sub/near-threshold 3D stacked ICs.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

Design and analysis of 3D IC-based low power stereo matching processors.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

Transient modeling of TSV-wire electromigration and lifetime analysis of power distribution network for 3D ICs.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Novel crack sensor for TSV-based 3D integrated circuits: design and deployment perspectives.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

On accurate full-chip extraction and optimization of TSV-to-TSV coupling elements in 3D ICs.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Electromigration study for multi-scale power/ground vias in TSV-based 3D ICs.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Full-chip multiple TSV-to-TSV coupling extraction and optimization in 3D ICs.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Power benefit study for ultra-high density transistor-level monolithic 3D ICs.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

How to reduce power in 3D IC designs: A case study with OpenSPARC T2 core.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

Thermal-reliable 3D clock-tree synthesis considering nonlinear electrical-thermal-coupled TSV model.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

High-density integration of functional modules using monolithic 3D-IC technology.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Block-level designs of die-to-wafer bonded 3D ICs and their design quality tradeoffs.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Test-TSV estimation during 3D-IC partitioning.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012
Distributed TSV Topology for 3-D Power-Supply Networks.
IEEE Trans. VLSI Syst., 2012

Variation-Aware Clock Network Design Methodology for Ultralow Voltage (ULV) Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

TSV Stress-Aware Full-Chip Mechanical Reliability Analysis and Optimization for 3-D IC.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

Backend dielectric reliability simulator for microprocessor system.
Microelectronics Reliability, 2012

Design Quality Trade-Off Studies for 3-D ICs Built With Sub-Micron TSVs and Future Devices.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

Transition delay fault testing of 3D ICs with IR-drop study.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Scan test of die logic in 3D ICs using TSV probing.
Proceedings of the 2012 IEEE International Test Conference, 2012


Design quality tradeoff studies for 3D ICs built with nano-scale TSVs and devices.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

A design tradeoff study with monolithic 3D integration.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Fast delay estimation with buffer insertion for through-silicon-via-based 3D interconnects.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

TSV array utilization in low-power 3D clock network design.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Electromigration-aware routing for 3D ICs with stress-aware EM modeling.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Ultra high density logic designs using transistor-level monolithic 3D integration.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Analysis of DC current crowding in through-silicon-vias and its impact on power integrity in 3D ICs.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Chip/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICs.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Exploiting die-to-die thermal coupling in 3D IC placement.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Slew-aware buffer insertion for through-silicon-via-based 3D ICs.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

TSV Stress-Aware ATPG for 3D Stacked ICs.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

Through-silicon-via-induced obstacle-aware clock tree synthesis for 3D ICs.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Design for manufacturability and reliability for TSV-based 3D ICs.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Block-level 3D IC design with through-silicon-via planning.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Integrated microarchitectural floorplanning and run-time controller for inductive noise mitigation.
ACM Trans. Design Autom. Electr. Syst., 2011

Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked ICs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Analysis and Design of Energy and Slew Aware Subthreshold Clock Systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Co-Optimization and Analysis of Signal, Power, and Thermal Interconnects in 3-D ICs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Impact of irregular geometries on low-k dielectric breakdown.
Microelectronics Reliability, 2011

Scan chain and power delivery network synthesis for pre-bond test of 3D ICs.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Impact of nano-scale through-silicon vias on the quality of today and future 3D IC designs.
Proceedings of the 2011 International Workshop on System Level Interconnect Prediction, 2011

Analysis of TSV-to-TSV coupling with high-impedance termination in 3D ICs.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Signal integrity analysis and optimization for 3D ICs.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Power-supply-network design in 3D integrated systems.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

TSV density-driven global placement for 3D stacked ICs.
Proceedings of the International SoC Design Conference, 2011

Variation-aware clock network design methodology for ultra-low voltage (ULV) circuits.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Designing 3D test wrappers for pre-bond and post-bond test of 3D embedded cores.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Electromigration modeling and full-chip reliability analysis for BEOL interconnect in TSV-based 3D ICs.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

A novel TSV topology for many-tier 3D power-delivery networks.
Proceedings of the Design, Automation and Test in Europe, 2011

Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC.
Proceedings of the 48th Design Automation Conference, 2011

Robust Clock Tree Synthesis with timing yield optimization for 3D-ICs.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
Methodology to determine the impact of linewidth variation on chip scale copper/low-k backend dielectric breakdown.
Microelectronics Reliability, 2010

SONOS-Type Flash Memory with HfO2 Thinner than 4 nm as Trapping Layer Using Atomic Layer Deposition.
IEICE Transactions, 2010

Through-silicon-via-aware delay and power prediction model for buffered interconnects in 3D ICs.
Proceedings of the International Workshop on System Level Interconnect Prediction Workshop, 2010

Through-silicon-via management during 3D physical design: When to add and how many?
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Design method and test structure to characterize and repair TSV defect induced signal degradation in 3D system.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Stress-driven 3D-IC placement with TSV keep-out zone and regularity study.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

TSV stress aware timing analysis with applications to 3D-IC layout optimization.
Proceedings of the 47th Design Automation Conference, 2010

Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

Power and slew-aware clock network design for through-silicon-via (TSV) based 3D ICs.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Buffered clock tree sizing for skew minimization under power and thermal budgets.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Timing analysis and optimization for 3D stacked multi-core microprocessors.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

A study of IR-drop noise issues in 3D ICs with through-silicon-vias.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

2009
Net-Sensitivity-Based Optimization of Large-Scale Field-Programmable Analog Array (FPAA) Placement and Routing.
IEEE Trans. on Circuits and Systems, 2009

Performance and Thermal-Aware Steiner Routing for 3-D Stacked ICs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs.
Proceedings of the 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), 2009

Slew-aware clock tree design for reliable subthreshold circuits.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Pre-bond testable low-power clock tree design for 3D stacked ICs.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Multi-functional interconnect co-optimization for fast and reliable 3D stacked ICs.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

A study of Through-Silicon-Via impact on the 3D stacked IC layout.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Decoupling capacitor planning with analytical delay model on RLC power grid.
Proceedings of the Design, Automation and Test in Europe, 2009

Co-design of signal, power, and thermal distribution networks for 3D ICs.
Proceedings of the Design, Automation and Test in Europe, 2009

Thermal optimization in multi-granularity multi-core floorplanning.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Global bus route optimization with application to microarchitectural design exploration.
Proceedings of the 26th International Conference on Computer Design, 2008

Buffered clock tree synthesis for 3D ICs under thermal variations.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Bus-aware microarchitectural floorplanning.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

A unified methodology for power supply noise reduction in modern microarchitecture design.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Introduction to special issue on demonstrable software systems and hardware platforms.
ACM Trans. Design Autom. Electr. Syst., 2007

Decoupling-Capacitor Planning and Sizing for Noise and Leakage Reduction.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Whitespace redistribution for thermal via insertion in 3D stacked ICs.
Proceedings of the 25th International Conference on Computer Design, 2007

Placement and routing of RF embedded passive designs in LCP substrate.
Proceedings of the 25th International Conference on Computer Design, 2007

Thermal-aware Steiner routing for 3D stacked ICs.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Rapid Prototyping of Large-scale Analog Circuits With Field Programmable Analog Array.
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture Profiling.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

An Efficient Computation of Statistically Critical Sequential Paths Under Retiming.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Multi-Objective Module Placement For 3-D System-On-Package.
IEEE Trans. VLSI Syst., 2006

Placement for large-scale floating-gate field-programable analog arrays.
IEEE Trans. VLSI Syst., 2006

Traffic: a novel geometric algorithm for fast wire-optimized floorplanning.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Block-level 3-D Global Routing With an Application to 3-D Packaging.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Profile-guided microarchitectural floor planning for deep submicron processor design.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Profile-Driven Instruction Mapping for Dataflow Architectures.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design.
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006

Integrated retiming and simultaneous Vdd/Vth scaling for total power minimization.
Proceedings of the 2006 International Symposium on Physical Design, 2006

3D floorplanning with thermal vias.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Optical routing for 3D system-on-package.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Microarchitectural floorplanning under performance and thermal tradeoff.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Statistical Bellman-Ford algorithm with an application to retiming.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Partitioning and placement for buildable QCA circuits.
JETC, 2005

Automatic cell placement for quantum-dot cellular automata.
Integration, 2005

Physical Design for 3D System on Package.
IEEE Design & Test of Computers, 2005

Reliability-aware floorplanning for 3D circuits.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

Mapping algorithm for large-scale field programmable analog array.
Proceedings of the 2005 International Symposium on Physical Design, 2005

Wire-driven microarchitectural design space exploration.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

QCA channel routing with wire crossing minimization.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

3D module placement for congestion and power noise reduction.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

MILP-based Placement and Routing for Dataflow Architecture.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Hierarchical Placement for Large-scale FPAA.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Placement for configurable dataflow architecture.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Wire congestion and thermal aware 3D global placement.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Retiming-based timing analysis with an application to mincut-based global placement.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

Edge separability-based circuit clustering with application to multilevel circuit partitioning.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

Multi-layer floorplanning for reliable system-on-package.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Simultaneous delay and power optimization in global placement.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Automatic cell placement for quantum-dot cellular automata.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Net and Pin Distribution for 3D Package Global Routing.
Proceedings of the 2004 Design, 2004

Profile-guided microarchitectural floorplanning for deep submicron processor design.
Proceedings of the 41th Design Automation Conference, 2004

Layer assignment for reliable system-on-package.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Performance-driven global placement via adaptive network characterization.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
A Novel Geometric Algorithm for Fast Wire-Optimized Floorplanning.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

2000
Physical Planning with Retiming.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Performance driven multi-level and multiway partitioning with retiming.
Proceedings of the 37th Conference on Design Automation, 2000

Performance driven multiway partitioning.
Proceedings of ASP-DAC 2000, 2000

Edge separability based circuit clustering with application to circuit partitioning.
Proceedings of ASP-DAC 2000, 2000

1998
Multiway partitioning with pairwise movement.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

1997
Large scale circuit partitioning with loose/stable net removal and signal flow based clustering.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997


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