Pruek Vanna-Iampikul

Orcid: 0000-0002-2897-7142

According to our database1, Pruek Vanna-Iampikul authored at least 10 papers between 2020 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Back-side Design Methodology for Power Delivery Network and Clock Routing.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

FastTuner: Transferable Physical Design Parameter Optimization using Fast Reinforcement Learning.
Proceedings of the 2024 International Symposium on Physical Design, 2024

2023
GNN-based Multi-bit Flip-flop Clustering and Post-clustering Design Optimization for Energy-efficient 3D ICs.
ACM Trans. Design Autom. Electr. Syst., September, 2023

Snap-3D: A Constrained Placement-Driven Physical Design Methodology for High Performance 3-D ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2023

Abisko: Deep codesign of an architecture for spiking neural networks using novel neuromorphic materials.
Int. J. High Perform. Comput. Appl., July, 2023

A 3D Implementation of Convolutional Neural Network for Fast Inference.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Glass Interposer Integration of Logic and Memory Chiplets: PPA and Power/Signal Integrity Benefits.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
Design Automation and Test Solutions for Monolithic 3D ICs.
ACM J. Emerg. Technol. Comput. Syst., 2022

2021
Snap-3D: A Constrained Placement-Driven Physical Design Methodology for Face-to-Face-Bonded 3D ICs.
Proceedings of the ISPD '21: International Symposium on Physical Design, 2021

2020
RTL-to-GDS Design Tools for Monolithic 3D ICs.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020


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