Chan-Wei Huang

According to our database, Chan-Wei Huang authored at least 3 papers between 2004 and 2009.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2009

Vernier Caliper and Equivalent-Signal Sampling for Built-In Jitter Measurement System.

Shu-Yu Jiang, Chan-Wei Huang, Yu-Lung Lo, Kuo-Hsing Cheng

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

2006

Self-sampled vernier delay line for built-in clock jitter measurement.

Kuo-Hsing Cheng, Chan-Wei Huang, Shu-Yu Jiang

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2004

64-bit Hybrid Dual-Threshold Voltage Power-Aware Conditional Carry Adder Design.

Kuo-Hsing Cheng, Shun-Wen Cheng, Chan-Wei Huang

Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 2004