Kuo-Hsing Cheng

Proceedings of the 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2019

2018

A Power-Saving Adaptive Equalizer With a Digital-Controlled Self-Slope Detection.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Low supply voltage and multiphase all-digital crystal-less clock generator.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2018

A Wide-Range All-Digital Delay-Locked Loop for Double Data Rate Synchronous Dynamic Random Access Memory Application.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017

A body sensor node SoC for ECG/EMG applications with compressed sensing and wireless powering.

[BibT_eX]

[DOI]

Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

2016

Proportional Static-Phase-Error Reduction for Frequency-Multiplier-Based Delay-Locked-Loop Architecture.

[BibT_eX]

[DOI]

Yo-Hao Tu

IEICE Trans. Electron., 2016

A 0.6-V 1.6-GHz 8-phase all digital PLL using multi-phase based TDC.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2016

A chaotically injected timing technique for ring-based oscillators.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

Low-voltage indoor energy harvesting using photovoltaic cell.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

Gm-C filter with automatic calibration scheme.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

2015

A Synchronous Mirror Delay with Duty-Cycle Tunable Technology.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

PVT Insensitive High-Resolution Time to Digital Converter for Intraocular Pressure Sensing.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

2014

A 0.9- to 8-GHz VCO With a Differential Active Inductor for Multistandard Wireline SerDes.

[BibT_eX]

[DOI]

Cheng-Liang Hung

Cihun-Siyong Alex Gong

Bo-Qian Jiang

Shi-Yang Sun

IEEE Trans. Circuits Syst. II Express Briefs, 2014

A low supply voltage synchronous mirror delay with quadrature phase output.

[BibT_eX]

[DOI]

Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

A 64-MHz∼640-MHz 64-phase clock generator.

[BibT_eX]

[DOI]

Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

2013

A low jitter delay-locked-loop applied for DDR4.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

Indoor energy harvesting using photovoltaic cell for battery recharging.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

External capacitorless low dropout linear regulator using cascode structure.

[BibT_eX]

[DOI]

Hong-Yi Huang

Cheng-Yu Chen

Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

2012

An All-Digital Clock Synchronization Buffer With One Cycle Dynamic Synchronizing.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

A 0.6-V 800-MHz All-Digital Phase-Locked Loop With a Digital Supply Regulator.

[BibT_eX]

[DOI]

Hong-Yi Huang

IEEE Trans. Circuits Syst. II Express Briefs, 2012

A 50 ns Verify Speed in Resistive Random Access Memory by Using a Write Resistance Tracking Circuit.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2012

A 6-Gb/s 3X-oversampling-like clock and data recovery in 0.13-µm CMOS technology.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Auto-calibration techniques in built-in jitter measurement circuit.

[BibT_eX]

[DOI]

Chih-Ping Cheng

Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2011

Built-in Jitter Measurement Circuit With Calibration Techniques for a 3-GHz Clock Generator.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

A High Precision Fast Locking Arbitrary Duty Cycle Clock Synchronization Circuit.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

A 0.5-V 0.4-2.24-GHz Inductorless Phase-Locked Loop in a System-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2011

A 6-GHz Built-in Jitter Measurement Circuit Using Multiphase Sampler.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2011

A 0.77 ps RMS Jitter 6-GHz Spread-Spectrum Clock Generator Using a Compensated Phase-Rotating Technique.

[BibT_eX]

[DOI]

Cheng-Liang Hung

Chih-Hsien Chang

IEEE J. Solid State Circuits, 2011

Fast-Write Resistive RAM (RRAM) for Embedded Applications.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2011

A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

All digital phase-locked loop using active inductor oscillator and novel locking algorithm.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A 0.06-psRMS SSC-induced jitter, ΔΣ-dithering-free, 6-GHz spread-spectrum clock generator for serial-ATA generation.

[BibT_eX]

[DOI]

Proceedings of the 37th European Solid-State Circuits Conference, 2011

2010

A 5-Gb/s Inductorless CMOS Adaptive Equalizer for PCI Express Generation II Applications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2010

A 3 GHz DLL-based clock generator with stuck locking protection.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Conference on Electronics, 2010

A CMOS adaptive equalizer using low-voltage zero generators technique.

[BibT_eX]

[DOI]

Proceedings of the 36th European Solid-State Circuits Conference, 2010

A loading effect insensitive and high precision clock synchronization circuit.

[BibT_eX]

[DOI]

Proceedings of the 36th European Solid-State Circuits Conference, 2010

A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

2009

A 2.5-GHz Built-in Jitter Measurement System in a Serial-Link Transceiver.

[BibT_eX]

[DOI]

Pei-Yi Jian

IEEE Trans. Very Large Scale Integr. Syst., 2009

Designing an Ultralow-Voltage Phase-Locked Loop Using a Bulk-Driven Technique.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2009

High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2009

Vernier Caliper and Equivalent-Signal Sampling for Built-In Jitter Measurement System.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

A Low Jitter Self-Calibration PLL for 10-Gbps SoC Transmission Links Application.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2009

Designing ultra-low voltage PLL Using a bulk-driven technique.

[BibT_eX]

[DOI]

Proceedings of the 35th European Solid-State Circuits Conference, 2009

0.5V 160-MHz 260uW all digital phase-locked loop.

[BibT_eX]

[DOI]

Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

2008

A High Linearity, Fast-Locking Pulsewidth Control Loop With Digitally Programmable Duty Cycle Correction for Wide Range Operation.

[BibT_eX]

[DOI]

Kai-Fei Chang

IEEE J. Solid State Circuits, 2008

Highly Accurate and Efficient Current-Mode PWM CMOS DC-DC Buck Converter with On-Chip Current-Sensing.

[BibT_eX]

[DOI]

Hsin-Hsin Ko

IEICE Trans. Electron., 2008

A compact and low-power SRAM with improved read static noise margin.

[BibT_eX]

[DOI]

Cihun-Siyong Alex Gong

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

A 1-V 10-bit 2GSample/s D/A converter based on precision current reference in 90-nm CMOS.

[BibT_eX]

[DOI]

Hsin-Hao Wang

Ding-Jyun Huang

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

A low jitter self-calibration PLL for 10Gbps SoC transmission links application.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

A wide-range DLL-based clock generator with phase error calibration.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

A high-accuracy and high-efficiency on-chip current sensing for current-mode control CMOS DC-DC buck converter.

[BibT_eX]

[DOI]

Hsin-Hsin Ko

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

A Spread-Spectrum Clock Generator Using Fractional PLL Controlled Delta-Sigma Modulator for Serial-ATA III.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

2007

A Fast-Lock Wide-Range Delay-Locked Loop Using Frequency-Range Selector for Multiphase Clock Generator.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2007

A Sub-1V Low-Power High-Speed Static Frequency Divider.

[BibT_eX]

[DOI]

Cheng-Liang Hung

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

All-Digital PLL Using Pulse-Based DCO.

[BibT_eX]

[DOI]

Hong-Yi Huang

Proceedings of the 14th IEEE International Conference on Electronics, 2007

A Phase Interpolator For Sub-1V And High Frequency For Clock And Data Recovery.

[BibT_eX]

[DOI]

Pei-Kai Tseng

Proceedings of the 14th IEEE International Conference on Electronics, 2007

A 100 MHz-1 GHz Adaptive Bandwidth PLL Using TDC Technique.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006

Improved 32-bit Conditional Sum Adder for Low-Power High-Speed Applications.

[BibT_eX]

[DOI]

J. Inf. Sci. Eng., 2006

64-bit Pipeline Carry Lookahead Adder Using all-n-transistor Tspc Logics.

[BibT_eX]

[DOI]

Wen-Shiuan Lee

J. Circuits Syst. Comput., 2006

Self-sampled vernier delay line for built-in clock jitter measurement.

[BibT_eX]

[DOI]

Chan-Wei Huang

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A 100MHz-1GHz adaptive bandwidth phase-locked loop in 90nm process.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A Variable Duty Cycle with High-Resolution Synchronous Mirror Delay.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on Electronics, 2006

Design of Self-Sampling Based ASK Demodulator for Implantable Microsystem.

[BibT_eX]

[DOI]

Cihun-Siyong Alex Gong

Proceedings of the 13th IEEE International Conference on Electronics, 2006

A fast-lock mixed-mode DLL with wide-range operation and multiphase outputs.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

2005

64-Bit High-Performance Power-Aware Conditional Carry Adder Design.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2005

A phase-detect synchronous mirror delay for clock skew-compensation circuits.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A 2GHz fully differential DLL-based frequency multiplier for high speed serial link circuit.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

The new approach of programmable pseudo fractional-N clock generator for GHz operation with 50% duty cycle.

[BibT_eX]

[DOI]

Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

2004

64-bit Hybrid Dual-Threshold Voltage Power-Aware Conditional Carry Adder Design.

[BibT_eX]

[DOI]

Chan-Wei Huang

Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 2004

64-bit Low Threshold Voltage High-Speed Conditional Carry Adder by Complementary Pass-Transistor Logi.

[BibT_eX]

[DOI]

Che-Yu Liao

Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phased-locked loop.

[BibT_eX]

[DOI]

Shu-Chang Kuo

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Static divided word matching line for low-power Content Addressable Memory design.

[BibT_eX]

Chia-Hung Wei

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A 14-bit, 200 MS/s digital-to-analog converter without trimming.

[BibT_eX]

Tsung-Shen Chen

Chia Ming Tu

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A fast-lock DLL with power-on reset circuit.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003

A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phase-locked loop.

[BibT_eX]

[DOI]

Cheng-Ming Ying

IEEE Trans. Circuits Syst. II Express Briefs, 2003

A Mixed-Mode Delay-Locked Loop for Wide-Range Operation and Multiphase Clock Generation.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June, 2003

A Robust Handshake for Asynchronous System.

[BibT_eX]

[DOI]

Wei-Chun Chang

Chia Ming Tu

Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June, 2003

A mixed-mode delay-locked loop for wide-range operation and multiphase outputs.

[BibT_eX]

[DOI]

Wen Fang Yu

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A new robust handshake for asymmetric asynchronous micro-pipelines.

[BibT_eX]

[DOI]

Yang-Han Lee

Wei-Chun Chang

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A dual-pulse-clock double edge triggered flip-flop for low voltage and high speed application.

[BibT_eX]

[DOI]

Yung-Hsiang Lin

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

BIST for clock jitter measurements.

[BibT_eX]

[DOI]

Zong-Shen Chen

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A CMOS charge pump for sub-2.0 V operation.

[BibT_eX]

[DOI]

Chung-Yu Chang

Chia-Hung Wei

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002

Prioritized Prime Implicant Patterns Puzzle for Novel Logic Synthesis and Optimization.

[BibT_eX]

[DOI]

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Influences of minimum cut plane properties on the mincut circuit partitioning problems.

[BibT_eX]

[DOI]

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

2001

A low-power high driving ability voltage control oscillator used in PLL.

[BibT_eX]

[DOI]

Chun-Fu Chung

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

ENISLE: an intuitive heuristic nearly optimal solution for mincut and ratio mincut partitioning.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A difference detector PFD for low jitter PLL.

[BibT_eX]

[DOI]

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

A CMOS low power voltage controlled oscillator with split-path controller.

[BibT_eX]

[DOI]

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

A 1.2 V 500 MHz 32-bit carry-lookahead adder.

[BibT_eX]

[DOI]

Wen-Shiuan Lee

Yung-Chong Huang

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Accurate current mirror with high output impedance.

[BibT_eX]

[DOI]

Chi-Che Chen

Chun-Fu Chung

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

A study on the relationship between initial node-edge pairs entropy and mincut circuit partitioning.

[BibT_eX]

[DOI]

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

2000

The design and implementation of DCT/IDCT chip with novel architecture.

[BibT_eX]

[DOI]

Chih-Sheng Huang

Chun-Pin Lin

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999

Dynamic Random Access Memory.

[BibT_eX]

[DOI]

Proceedings of the VLSI Handbook., 1999

The suggestion for CFS CMOS buffer.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

The novel efficient design of XOR/XNOR function for adder applications.

[BibT_eX]

[DOI]

Chih-Sheng Huang

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

1998

Low voltage low power high-speed BiCMOS multiplier.

[BibT_eX]

[DOI]

Yu-Kwang Yeha

Farn-Sou Lian

Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

1996

A 1.2 V CMOS multiplier using low-power current-sensing complementary pass-transistor logic.

[BibT_eX]

[DOI]

Yu-Yee Liow

Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

1995

A New CMOS Current-Sensing Complementary Pass-Transistor Logic (CSCPTL) for High-Speed Low-Voltage Applications.

[BibT_eX]

[DOI]

Chung-Yu Wu

Jr-Houng Lu

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Low-Voltage Low-Power CMOS True-Single-Phase Clocking Scheme with Locally Asynchronous Logic Circuits.

[BibT_eX]

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994

Feedback-Controlled Enhance-Pull-Down BiCMOS for Sub-3-V Digital Circuit.

[BibT_eX]

[DOI]

Yuh-Kuang Tseng