Shun-Wen Cheng

According to our database, Shun-Wen Cheng authored at least 17 papers between 2001 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2018

Universal CMOS Diamond-Graph Circuit for Embedded Computing.

Shun-Wen Cheng, Chun-Pin Lin, Chi-Shi Chen, Wei-Chang Tsai

Proceedings of the 31st IEEE International System-on-Chip Conference, 2018

2016

Self-dual diamond-graph CMOS H-bridge logic family.

Shun-Wen Cheng

Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

A driver's physiological monitoring system based on photodiode sensor with reflective optics element.

Chun-Yao Shih, Shun-Wen Cheng

Proceedings of the IEEE International Conference on Vehicular Electronics and Safety, 2016

2014

Opportunities for Persuasive Technology to Motivate Heavy Computer Users for Stretching Exercise.

Yong-Xiang Chen, Siek-Siang Chiang, Shu-Yun Chih, Wen-Ching Liao, Shih-Yao Lin, Shang-Hua Yang, Shun-Wen Cheng, Shih-Sung Lin, Yu-Shan Lin, Ming-Sui Lee, Jau-Yih Tsauo, Cheng-Min Jen, Chia-Shiang Shih, King-Jen Chang, Yi-Ping Hung

Proceedings of the Persuasive Technology - 9th International Conference, 2014

2010

Over complementary MOS logic for don't care conditions.

Shun-Wen Cheng

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2008

H-tree CMOS logic circuit.

Shun-Wen Cheng

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2006

Improved 32-bit Conditional Sum Adder for Low-Power High-Speed Applications.

Kuo-Hsing Cheng, Shun-Wen Cheng

J. Inf. Sci. Eng., 2006

64-bit Pipeline Carry Lookahead Adder Using all-n-transistor Tspc Logics.

Kuo-Hsing Cheng, Shun-Wen Cheng, Wen-Shiuan Lee

J. Circuits Syst. Comput., 2006

2005

64-Bit High-Performance Power-Aware Conditional Carry Adder Design.

Kuo-Hsing Cheng, Shun-Wen Cheng

IEICE Trans. Electron., 2005

2004

64-bit Hybrid Dual-Threshold Voltage Power-Aware Conditional Carry Adder Design.

Kuo-Hsing Cheng, Shun-Wen Cheng, Chan-Wei Huang

Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 2004

64-bit Low Threshold Voltage High-Speed Conditional Carry Adder by Complementary Pass-Transistor Logi.

Kuo-Hsing Cheng, Shun-Wen Cheng, Che-Yu Liao

Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

2003

A high-speed magnitude comparator with small transistor count.

Shun-Wen Cheng

Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

Arbitrary long digit integer sorter HW/SW co-design.

Shun-Wen Cheng

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Prioritized Prime Implicant Patterns Puzzle for Novel Logic Synthesis and Optimization.

Kuo-Hsing Cheng, Shun-Wen Cheng

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Influences of minimum cut plane properties on the mincut circuit partitioning problems.

Kuo-Hsing Cheng, Shun-Wen Cheng

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

2001

ENISLE: an intuitive heuristic nearly optimal solution for mincut and ratio mincut partitioning.

Shun-Wen Cheng, Kuo-Hsing Cheng

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A study on the relationship between initial node-edge pairs entropy and mincut circuit partitioning.

Kuo-Hsing Cheng, Shun-Wen Cheng

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001