Chao You

Orcid: 0000-0001-8501-1945

According to our database1, Chao You authored at least 37 papers between 2002 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
The prognostic value and immune landscaps of m6A/m5C-related lncRNAs signature in the low grade glioma.
BMC Bioinform., December, 2023

Graph Representation Learning Meets Computer Vision: A Survey.
IEEE Trans. Artif. Intell., February, 2023

Boundary-Aware Multiscale Learning Perception for Remote Sensing Image Segmentation.
IEEE Trans. Geosci. Remote. Sens., 2023

Brain-Inspired Remote Sensing Interpretation: A Comprehensive Survey.
IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2023

2020
Primary Neuroendocrine Carcinoma of the Breast: Mammographic, Ultrasound, and Magnetic Resonance Imaging Findings.
J. Medical Imaging Health Informatics, 2020

2019
Hypergraph partitions.
CoRR, 2019

2015
High-Speed Reconfigurable Circuits for Multirate Systems in SiGe HBT Technology.
Proc. IEEE, 2015

2012
Multi-attribute decision making method with intuitionistic fuzzy sets.
Proceedings of the 9th International Conference on Fuzzy Systems and Knowledge Discovery, 2012

Towards Online Localization and Recovery for Faulty Components in Component-Based Applications.
Proceedings of the 36th Annual IEEE Computer Software and Applications Conference, 2012

2011
Impedance-Based Wireless Sensor Network for Metal-Protective Coating Evaluation.
Int. J. Meas. Technol. Instrum. Eng., 2011

A Policy-Based Framework for Automated Service Level Agreement Negotiation.
Proceedings of the IEEE International Conference on Web Services, 2011

Towards a Constraint-Based Framework for Dynamic Business Process Adaptation.
Proceedings of the IEEE International Conference on Services Computing, 2011

2010
Design of a Reconfigurable Pulsed Quad-Cell for Cellular-Automata-Based Conformal Computing.
Int. J. Reconfigurable Comput., 2010

0.18 μm CMOS integrated circuit design for impedance-based structural health monitoring.
IET Circuits Devices Syst., 2010

Enabling on Demand Deployment of Middleware Services in Componentized Middleware.
Proceedings of the Component-Based Software Engineering, 13th International Symposium, 2010

2009
Towards a dynamic and adaptable application server.
Proceedings of the First Asia-Pacific Symposium on Internetware, 2009

Towards a Well Structured and Dynamic Application Server.
Proceedings of the 33rd Annual IEEE International Computer Software and Applications Conference, 2009

Towards Dynamic Component Updating: A Flexible and Lightweight Approach.
Proceedings of the 33rd Annual IEEE International Computer Software and Applications Conference, 2009

Extracting Behavioral Models from WS-BPEL Processes for Service Discovery.
Proceedings of the 2009 IEEE International Conference on Services Computing (SCC 2009), 2009

2008
Load balance and energy efficient data gathering in wireless sensor networks.
Wirel. Commun. Mob. Comput., 2008

A Cellular Automata ASIC for Conformal Computing.
Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2008

2007
A 12-Gb/s DEMUX Implemented With SiGe High-Speed FPGA Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Silicon germanium programmable circuits for gigahertz applications.
IET Circuits Devices Syst., 2007

2005
A 5-10GHz SiGe BiCMOS FPGA with new configurable logic block.
Microprocess. Microsystems, 2005

Multi-ghz Sige Bicmos Fpgas with New Architecture and Novel Power Management Techniques.
J. Circuits Syst. Comput., 2005

A 10 GHz 4: 1 MUX and 1: 4 DEMUX implemented by a Gigahertz SiGe FPGA for fast ADC.
Integr., 2005

A High Speed Reconfigurable Gate Array for Gigahertz Applications.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

A 11 GHz FPGA with Test Applications.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

2004
The 10GHz 4: 1 MUX and 1: 4 DEMUX implemented via the gigahertz SiGe FPGA.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

The gigahertz FPGA: design consideration and applications.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

2003
A 5-20 GHz, low power FPGA implemented by SiGe HBT BiCMOS technology.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

Gigahertz FPGA by SiGe BiCMOS Technology for Low Power, High Speed Computing with 3-D Memory.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

A four-bit full adder implemented on fast SiGe FPGAs with novel power control scheme.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

A scalable 2 V, 20 GHz FPGA using SiGe HBT BiCMOS technology.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

A Novel Multi-Speed, Power Saving Architecture for SiGe HBT FPGA.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, June 23, 2003

2002
Gigahertz SiGe BiCMOS FPGAs with new architectures and novel power management schemes.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

Fast SiGe HBT BiCMOS FPGAs with New Architecture and Power Saving Techniques.
Proceedings of the Field-Programmable Logic and Applications, 2002


  Loading...