Russell P. Kraft

According to our database1, Russell P. Kraft authored at least 41 papers between 1979 and 2015.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2015
140 Gb/s Serializer Using Clock Doublers in 90 nm SiGe Technology.
IEEE J. Solid State Circuits, 2015

Thermal Modeling of 3-D Stacked DRAM Over SiGe HBT BiCMOS CPU.
IEEE Access, 2015

2014
Design of High-Speed Register Files Using SiGe HBT BiCMOS Technology.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

Design of BiCMOS SRAMs for high-speed SiGe applications.
IET Circuits Devices Syst., 2014

2012
A three-dimensional DRAM using floating body cell in FDSOI devices.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2011
Carry Chains for Ultra High-Speed SiGe HBT Adders.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Reconfigurable 40 GHz BiCMOS uniform delay crossbar switch for broadband and wide tuning range narrowband applications.
IET Circuits Devices Syst., 2011

2010
A 3-D Cache With Ultra-Wide Data Bus for 3-D Processor-Memory Integration.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Correction to "A 40 GS/s Time Interleaved ADC Using SiGe BiCMOS Technology".
IEEE J. Solid State Circuits, 2010

A 40 Gs/s Time Interleaved ADC Using SiGe BiCMOS Technology.
IEEE J. Solid State Circuits, 2010

2009
Mitigating Memory Wall Effects in High-Clock-Rate and Multicore CMOS 3-D Processor Memory Stacks.
Proc. IEEE, 2009

Thermal analysis for a SiGe HBT 40 watt 32 GHz clock 3D memory processor chip stack using diamond heat spreader layers.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

2007
A 12-Gb/s DEMUX Implemented With SiGe High-Speed FPGA Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2007

52 Gb/s 16: 1 transmitter in 0.13 μm SiGe BiCMOS technology.
IET Circuits Devices Syst., 2007

Silicon germanium programmable circuits for gigahertz applications.
IET Circuits Devices Syst., 2007

Amdahl's figure of merit, SiGe HBT BiCMOS, and 3D chip stacking.
Proceedings of the 25th International Conference on Computer Design, 2007

2005
SiGe HBT Microprocessor Core Test Vehicle.
Proc. IEEE, 2005

A 5-10GHz SiGe BiCMOS FPGA with new configurable logic block.
Microprocess. Microsystems, 2005

Multi-ghz Sige Bicmos Fpgas with New Architecture and Novel Power Management Techniques.
J. Circuits Syst. Comput., 2005

A 10 GHz 4: 1 MUX and 1: 4 DEMUX implemented by a Gigahertz SiGe FPGA for fast ADC.
Integr., 2005

Predicting the Performance of a 3D Processor-Memory Chip Stack.
IEEE Des. Test Comput., 2005

12-23 GHz Ultra Wide Tuning Range Voltage-Controlled Ring Oscillator with Hybrid Control Schemes.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

A High Speed Reconfigurable Gate Array for Gigahertz Applications.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

A 11 GHz FPGA with Test Applications.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

2004
The 10GHz 4: 1 MUX and 1: 4 DEMUX implemented via the gigahertz SiGe FPGA.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

The gigahertz FPGA: design consideration and applications.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

2003
A 5-20 GHz, low power FPGA implemented by SiGe HBT BiCMOS technology.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

3D direct vertical interconnect microprocessors test vehicle.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

Gigahertz FPGA by SiGe BiCMOS Technology for Low Power, High Speed Computing with 3-D Memory.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

A four-bit full adder implemented on fast SiGe FPGAs with novel power control scheme.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

A scalable 2 V, 20 GHz FPGA using SiGe HBT BiCMOS technology.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

A Novel Multi-Speed, Power Saving Architecture for SiGe HBT FPGA.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, June 23, 2003

2002
Gigahertz SiGe BiCMOS FPGAs with new architectures and novel power management schemes.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

Fast SiGe HBT BiCMOS FPGAs with New Architecture and Power Saving Techniques.
Proceedings of the Field-Programmable Logic and Applications, 2002

Gigahertz FPGAs with New Power Saving Techniques and Decoding Logic.
Proceedings of the 4th NASA / DoD Workshop on Evolvable Hardware (EH 2002), 2002

2001
Gigahertz Reconfigurable Computing Using SiGe HBT BiCMOS FPGAs.
Proceedings of the Field-Programmable Logic and Applications, 2001

2000
A 2-GHz clocked AlGaAs/GaAs HBT byte-slice datapath chip.
IEEE J. Solid State Circuits, 2000

1999
Accurate high-speed performance prediction for full differential current-mode logic: the effect of dielectric anisotropy.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

1998
A very wide bandwidth digital VCO using quadrature frequency multiplication and division implemented in AlGaAs/GaAs HBT's.
IEEE Trans. Very Large Scale Integr. Syst., 1998

1982
Homomorphic signal dereverberation for a phased array imaging system.
Proceedings of the IEEE International Conference on Acoustics, 1982

1979
Minimax optimization of two-dimensional focused nonuniformly spaced arrays.
Proceedings of the IEEE International Conference on Acoustics, 1979


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