Cheng-Tai Yeh

According to our database, Cheng-Tai Yeh authored at least 2 papers in 2012.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2012

An ultra Low-voltage/Power-Efficient All-Digital Delay Locked Loop in 55 nm CMOS Technology.

Chun-Yuan Cheng, Jinn-Shyan Wang, Cheng-Tai Yeh

J. Circuits Syst. Comput., 2012

Design of a 2.5-GHz, 3-ps jitter, 8-locking-cycle, all-digital delay-locked loop with cycle-by-cycle phase adjustment.

Chun-Yuan Cheng, Jinn-Shyan Wang, Cheng-Tai Yeh, Jenn-Shyan Sheu

Proceedings of the Symposium on VLSI Circuits, 2012