Chun-Yuan Cheng
According to our database1,
Chun-Yuan Cheng
authored at least 25 papers
between 1994 and 2023.
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Bibliography
2023
Proceedings of the International Conference on System Science and Engineering, 2023
2015
An All-Digital Delay-Locked Loop Using an In-Time Phase Maintenance Scheme for Low-Jitter Gigahertz Operations.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
A Wide-Range, Low-Power, All-Digital Delay-Locked Loop With Cyclic Half-Delay-Line Architecture.
IEEE J. Solid State Circuits, 2015
J. Inf. Sci. Eng., 2015
2014
A Modified Preventive Maintenance Model with Degradation Rate Reduction in a Finite Time Span.
Proceedings of the ICINCO 2014 - Proceedings of the 11th International Conference on Informatics in Control, Automation and Robotics, Volume 2, Vienna, Austria, 1, 2014
A 3 MHz-to-1.8 GHz 94 μW-to-9.5 mW 0.0153-mm<sup>2</sup> all-digital delay-locked loop in 65-nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
2012
An ultra Low-voltage/Power-Efficient All-Digital Delay Locked Loop in 55 nm CMOS Technology.
J. Circuits Syst. Comput., 2012
Annotating photographs of places of interest in Taiwan - a multifaceted photo summarisation method based on TELDAP.
Int. J. Humanit. Arts Comput., 2012
Design of a 2.5-GHz, 3-ps jitter, 8-locking-cycle, all-digital delay-locked loop with cycle-by-cycle phase adjustment.
Proceedings of the Symposium on VLSI Circuits, 2012
2011
The Near-Optimal Preventive Maintenance Policies for a Repairable System with a Finite Life Time by Using Simulation Methods.
J. Comput., 2011
Proceedings of the 9th NTCIR Workshop Meeting on Evaluation of Information Access Technologies: Information Retrieval, 2011
The impacts of common cause failures for two-unit parallel systems from RAMS+C point of view.
Proceedings of the 2011 IEEE International Conference on Industrial Engineering and Engineering Management (IEEM), 2011
Proceedings of the Seventh International Conference on Natural Computation, 2011
ADDLL/VDD-biasing co-design for process characterization, performance calibration, and clock synchronization in variation-tolerant designs.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
2010
A Duty-Cycle-Distortion-Tolerant Half-Delay-Line Low-Power Fast-Lock-in All-Digital Delay-Locked Loop.
IEEE J. Solid State Circuits, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
Random Variates Generating Methods of Time-between-failures for the Repairable Systems under Age-reduction Preventive Maintenance.
Proceedings of the ICINCO 2009, 2009
2008
The Periodic Maintenance Policy for a Weibull Life-Time System with Degradation Rate Reduction under Reliability Limit.
Asia Pac. J. Oper. Res., 2008
2007
Proceedings of the IEEE International Conference on Systems, 2007
2006
Proceedings of the IEEE International Conference on Systems, 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2005
Comput. Oper. Res., 2005
2003
Comput. Oper. Res., 2003
2002
The total completion time open shop scheduling problem with a given sequence of jobs on one machine.
Comput. Oper. Res., 2002
1994
Generating correlated random variates based on an analogy between correlation and force.
Proceedings of the 26th conference on Winter simulation, 1994