Chenghao Zhang

According to our database, Chenghao Zhang authored at least 10 papers between 2021 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

A 40-GS/s 8-bit Time-Interleaved ADC Featuring SFDR-Enhanced Sampling and Power-Efficient Time-Domain Quantization in 28-nm CMOS.

Chenghao Zhang, Maliang Liu, Yuan Chang, Yihang Yang, Jinhai Xiao, Yintang Yang, Yong Chen

IEEE J. Solid State Circuits, May, 2026

A 19.4-fs_RMS Jitter 0.1-to-44-GHz Cryo-CMOS Fractional-N CP-PLL Featuring Automatic Bleed Calibration for Quantum Computing.

Jinhai Xiao, Yong Chen, Ningyi Zhang, Xiaolong Liu, Rui Liu, Junao Zhu, Chenghao Zhang, Peng Luo, Maliang Liu, Yintang Yang, Xiaohua Ma, Yue Hao

IEEE J. Solid State Circuits, May, 2026

A 10-Bit 2-GS/s Voltage-Time-Pipelined Hybrid ADC with One-Hot Background Calibration Scoring > 60-dB SFDR in 28-nm CMOS.

Yuan Chang, Chenghao Zhang, Yihang Yang, Maliang Liu, Yintang Yang, Yong Chen

Circuits Syst. Signal Process., February, 2026

2025

An 8-Bit 4-GS/s Single-Channel Two-Step ADC Featuring Non-Symmetrical Pipeline Timing and Hybrid-Loop Amplifier.

Chenghao Zhang, Maliang Liu, Yuan Chang, Yihang Yang, Jinhai Xiao, Yintang Yang, Yuanjin Zheng, Yong Chen

IEEE Trans. Very Large Scale Integr. Syst., October, 2025

A 6.86mW 1.5 GS/s 9 b Pipelined SAR ADC with TDC-Assisted Residue Quantization.

Chenghao Zhang, Maliang Liu, Yuan Chang, Yihang Yang, Jinhai Xiao, Yintang Yang, Yuanjin Zheng

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

2023

A 0.004-mm² 3.65-mW 7-Bit 2-GS/s Single-Channel GRO-Based Time-Domain ADC Incorporating Dead-Zone Elimination and On-Chip Folding-Offset Calibration in 28-nm CMOS.

Chenghao Zhang, Jiangbo Wei, Yong Chen, Maliang Liu, Yintang Yang

IEEE J. Solid State Circuits, November, 2023

A Reconfigurable 8-to-10-bit 20-to-5-GS/s time-interleaved time-domain ADC.

Jiangbo Wei, Chenghao Zhang, Xinyu Wang, Yuan Chang, Maliang Liu

Microelectron. J., 2023

2022

A 11-Bit 1-GS/s 14.9mW Hybrid Voltage-Time Pipelined ADC With Gain Error Calibration.

Jiangbo Wei, Chenghao Zhang, Maliang Liu

IEEE Trans. Circuits Syst. II Express Briefs, 2022

A 12-bit 1.25 GS/s RF sampling pipelined ADC using a bandwidth-expanded residue amplifier with bias-free gain-boost technique.

Chenghao Zhang, Jiangbo Wei, Yihang Yang, Maliang Liu

Microelectron. J., 2022

2021

An ECG Automatic Detection System with Baseline Drift Removal Based on SG Filter.

Jiangbo Wei, Chenghao Zhang, Jiaji Ma, Zhihang Li, Maliang Liu

Proceedings of the 14th IEEE International Conference on ASIC, 2021